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  Semiconductor device including a capacitanceUSPTO Application #: 20070296009Title: Semiconductor device including a capacitance Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168). (end of abstract) Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C. - Alexandria, VA, US Inventors: Shigenobu MAEDA, Takashi IPPOSHI, Yuuichi HIRANO USPTO Applicaton #: 20070296009 - Class: 257296000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell) The Patent Description & Claims data below is from USPTO Patent Application 20070296009. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having an insulated gate type transistor and an insulated gate type capacitance and a method of manufacturing the semiconductor device. [0003] 2. Description of the Background Art [0004] In a transistor having a gate length of a subquarter micron or less, a pocket injecting process for forming a pocket region is executed in order to suppress a short channel effect. The pocket injection is also referred to as NUDC (Non Uniformly Doped Channel). [0005] FIG. 52 is a sectional view showing the pocket injecting process. As shown in FIG. 52, in the formation of a CMOS transistor, an NMOS formation region A11 and a PMOS formation region A12 are isolated from each other through an isolating film 102 provided in an upper layer portion of a semiconductor substrate 101. [0006] In the NMOS formation region A11, a gate oxide film 112 and a gate electrode 113 are formed on a surface of a P well region 111 and a P-type impurity ion 103 is implanted and diffused by using the gate electrode 113 as a mask. Consequently, a P-type impurity implantation region 119 to be a pocket region of an NMOS transistor is formed. [0007] In the PMOS formation region A12, similarly, a gate oxide film 122 and a gate electrode 123 are formed on a surface of an N well region 121 and an N-type impurity ion 104 is implanted and diffused by using the gate electrode 123 as a mask. Consequently, an N-type impurity implantation region 129 to be a pocket region of a PMOS transistor is formed. [0008] More specifically, in the pocket injecting process, an impurity of the same conductivity type as that of a channel region of each MOS transistor is implanted into each of the NMOS formation region A11 and the PMOS formation region A12. In the pocket injecting process, the distribution of an impurity in a direction of a channel length becomes nonuniform and an effective channel impurity concentration is increased when a gate length becomes smaller. As a result, it is possible to suppress the short channel effect. [0009] FIG. 53 is a sectional view showing a state in which a CMOS transistor is finished after the pocket injecting process. [0010] As shown in FIG. 53, in the NMOS formation region A11, N.sup.+ source-drain regions 114 and 114 are formed to interpose therebetween a channel region provided under the gate electrode 113 and tip regions opposed to each other between the N.sup.+ source-drain regions 114 and 114 are extension portions 114e, respectively. [0011] In a vicinal region of the extension portion 114e, the P-type impurity implantation region 119 remains as a P.sup.- pocket region 117 from the extension portion 114e to a part of the channel region. Moreover, side walls 116 and 116 are formed on both side surfaces of the gate electrode 113, respectively. [0012] Thus, an NMOS transistor Q11 is formed by the gate oxide film 112, the gate electrode 113, the N.sup.+ source-drain region 114, the side wall 116 and the P.sup.- pocket region 117. [0013] In the PMOS formation region A12, P.sup.+ source-drain regions 124 and 124 are formed to interpose therebetween a channel region provided under the gate electrode 123 and tip regions opposed to each other between the P.sup.+ source-drain regions 124 and 124 are extension portions 124e, respectively. [0014] In a vicinal region of the extension portion 124e, the N-type impurity implantation region 129 remains as an N.sup.- pocket region 127 from the extension portion 124e to a part of the channel region. Moreover, side walls 126 and 126 are formed on both side surfaces of the gate electrode 123, respectively. [0015] Thus, a PMOS transistor Q12 is formed by the gate oxide film 122, the gate electrode 123, the P.sup.+ source-drain region 124, the side wall 126 and the N.sup.- pocket region 127. [0016] On the other hand, in a high-frequency analog circuit or a high-speed digital circuit, it is necessary to manufacture an LC type VCO (Voltage Controlled Oscillator) by using an inductor (L) and a variable capacitance (C). [0017] In the case in which the variable capacitance to be an insulated gate type capacitance which has a small loss is to be obtained by utilizing the structure of the MOS transistor, it is necessary to generate an accumulation type variable capacitance in which impurities in a substrate (a body region) and a fetch electrode portion have the same conductivity type. [0018] FIG. 54 is a sectional view showing a structure of the accumulation type variable capacitance. As shown in FIG. 54, in the formation of the accumulation type variable capacitance, a P-type variable capacitance formation region A13 and an N-type variable capacitance formation region A14 are isolated from each other through an isolating film 102 provided in an upper layer portion of a semiconductor substrate 101. [0019] In the P-type variable capacitance formation region A13, P.sup.+ fetch electrode regions 134 and 134 are formed to interpose therebetween a channel region provided under a gate electrode 133 and tip regions opposed to each other between the P.sup.+ fetch electrode regions 134 and 134 are extension portions 134e, respectively. [0020] In a vicinal region of the extension portion 134e, an N.sup.- pocket region 137 is formed from the extension portion 134e to a part of the channel region. Moreover, side walls 136 and 136 are formed on both side surfaces of the gate electrode 133, respectively. [0021] Thus, a P-type variable capacitance C11 is formed by a gate oxide film 132, the gate electrode 133, the P.sup.+ fetch electrode region 134, the side wall 136 and the N.sup.- pocket region 137. In other words, the P-type variable capacitance C11 acts as an insulated gate type capacitance in which the P.sup.+ fetch electrode region 134 is set to one of electrodes, the gate electrode 133 is set to the other electrode and the gate oxide film 132 is set to an interelectrode insulating film. [0022] In the N-type variable capacitance formation region A14, N.sup.+ fetch electrode regions 144 and 144 are formed to interpose therebetween a channel region provided under a gate electrode 143 and tip regions opposed to each other between the N.sup.+ fetch electrode regions 144 and 144 are extension portions 144e, respectively. [0023] In a vicinal region of the extension portion 144e, a P.sup.- pocket region 147 is formed from the extension portion 144e to a part of the channel region. Moreover, side walls 146 and 146 are formed on both side surfaces of the gate electrode 143, respectively. Continue reading... Full patent description for Semiconductor device including a capacitance Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Semiconductor device including a capacitance patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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