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Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity typeUSPTO Application #: 20060145290Title: Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type Abstract: A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area. (end of abstract) Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C. - Alexandria, VA, US Inventors: Hideki Okumura, Hitoshi Kobayashi, Masanobu Tsuchitani, Akihiko Osawa, Wataru Saito, Masakazu Yamaguchi, Ichiro Omura USPTO Applicaton #: 20060145290 - Class: 257529000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Integrated Circuit Structure With Electrically Isolated Components, Passive Components In Ics, Including Programmable Passive Component (e.g., Fuse)
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