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  Semiconductor device having sufficient process margin and method of forming sameUSPTO Application #: 20070190812Title: Semiconductor device having sufficient process margin and method of forming same Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed. (end of abstract)
Agent: Marger Johnson & Mccollom, P.C. - Portland, OR, US Inventors: Man-Hyoung RYOO, Gi-Sung YEO, Si-Hyeung LEE, Gyu-Chul KIM, Sung-Gon JUNG, Chang-Min PARK, Hoo-Sung CHO USPTO Applicaton #: 20070190812 - Class: 438FOR189 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20070190812. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of U.S. patent application Ser. No. 10/892,588, filed on Jul. 15, 2004, now pending, which claims priority under 35 U.S.C. .sctn. 119 to Korean Patent Application No. 2003-48223, filed on Jul. 15, 2003, the contents of which are herein incorporated by reference in their entirety for all purposes. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, an SRAM device and a method of manufacturing an SRAM device. More particularly, the present invention relates to a semiconductor device, a method of manufacturing a semiconductor device, an SRAM device and a method of manufacturing an SRAM device having a sufficient process margin. [0004] 2. Description of the Related Art [0005] Generally, semiconductor memory devices may be categorized as either a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device in accordance with memory type. The SRAM device has a rapid speed, low power consumption, and a simply operated structure. Accordingly, the SRAM device is currently noticed in a semiconductor memory field. Information stored in the DRAM device is periodically refreshed. A periodical refresh of information stored in the SRAM device is, however, not necessary. [0006] A typical SRAM device includes two pull-down elements, two pass elements, and two pull-up elements. The SRAM device may be classified as either a full CMOS type, a high load resistor (HLR) type, or a thin film transistor (TFT) type in accordance with the configuration of the pull-up element. A p-channel bulk MOSFET is used as the pull-up element in the full CMOS type. A polysilicon layer having a high resistance value is used as the pull-up element in the HLR type. A p-channel polysilicon TFT is used as the pull-up element in the TFT type. The SRAM device having the full CMOS type of a cell has a low standby current, and also stably operates compared to the SRAM having other types of cells. FIG. 1 is a circuit illustrating a conventional full CMOS type SRAM cell. [0007] Referring to FIG. 1, a conventional SRAM cell includes first and second pass transistors Q1 and Q2 for electrically connecting first and second bit lines BL1 and BL2 to first and second memory cell nodes Nd1 and Nd2, respectively, a PMOS type pull-up transistor Q5 electrically connected between the first memory cell node Nd1 and a positive supply voltage Vdd, and an NMOS type pull-down transistor Q3 electrically connected between the first memory cell node Nd1 and a negative supply voltage Vss. The PMOS type pull-up transistor Q5 and the NMOS type pull-down transistor Q3 are controlled by a signal outputted from the second memory cell node Nd2 to thereby provide the positive supply voltage Vdd or the negative supply voltage Vss to the first memory cell node Nd1. [0008] The conventional SRAM cell further includes a PMOS type pull-up transistor Q6 electrically connected between the positive supply voltage Vdd and the second memory cell node Nd2, and an NMOS type pull-down transistor Q4 electrically connected between the second memory node Nd2 and the negative supply voltage Vss. The PMOS type pull-up transistor Q6 and the NMOS type pull-down transistor Q4 are controlled by a signal outputted from the first memory cell node Nd1 to thereby provide the positive supply voltage Vdd or the negative supply voltage Vss to the second memory cell node Nd2. [0009] The first pass transistor Q1, the NMOS type pull-down transistor Q3 and the PMOS pull-up transistor Q5 are interconnected at the first memory cell node Nd1. The second pass transistor Q2, the NMOS type pull-down transistor Q4 and the PMOS pull-up transistor Q6 are interconnected at the second memory cell node Nd2. [0010] The full CMOS type SRAM cell includes the NMOS type transistors Q1, Q2, Q3 and Q4, and the PMOS type transistors Q5 and Q6. When the NMOS and PMOS type transistors are disposed adjacently to each other in one cell, a latch-up and the like may occur, which causes an excessive current to flow between a positive supply voltage line and a negative supply voltage line. [0011] To prevent the occurrence of the latch-up, active patterns are disposed so that pitches between the active patterns can have more than two sizes. Namely, in such arrangement of the active patterns, a pitch between an active pattern in which the PMOS type transistor is formed and an active pattern in which the NMOS type transistor is formed is relatively lengthened to perform an entirely elemental isolation between the PMOS and NMOS transistors. On the contrary, a pitch between active patterns in which identical MOS type transistors are disposed is relatively shortened. [0012] Thus, in the conventional full CMOS type SRAM cell, since the pitches between the active patterns have more than two sizes that are different from each other, pitches between patterns and pitches between contacts formed on the active pattern, respectively, are also more than two sizes. When the pitches between the patterns formed by the same process are varied as described above, a margin of a photolithography process for forming the patterns is determined based on the minimal one of the pitches between the patterns. Accordingly, the process margin is greatly decreased so that a probability of failures in forming the patterns may be high. Furthermore, it may be difficult to manufacture a highly-integrated semiconductor device by shrinking a cell size of the semiconductor device. [0013] Embodiments of the invention address these and other disadvantages of the conventional art. SUMMARY OF THE INVENTION [0014] The present invention provides a semiconductor device having an increased margin of a photolithography process. [0015] The present invention also provides a method of manufacturing a semiconductor device having an increased margin of a photolithography process. [0016] The present invention still also provides an SRAM device having an increased margin of a photolithography process. [0017] The present invention still also provides a method of manufacturing an SRAM device having an increased margin of a photolithography process. BRIEF DESCRIPTION OF THE DRAWINGS [0018] The above and other features and advantages of the invention will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings. [0019] FIG. 1 is a circuit diagram illustrating a conventional full CMOS type SRAM cell. [0020] FIG. 2 is a layout diagram illustrating active patterns and gate patterns of a full CMOS type SRAM cell in accordance with some embodiments of the invention. Continue reading... Full patent description for Semiconductor device having sufficient process margin and method of forming same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Semiconductor device having sufficient process margin and method of forming same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. 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