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Semiconductor device having an integrated, self-regulated pwm current and power limiter and method




Title: Semiconductor device having an integrated, self-regulated pwm current and power limiter and method.
Abstract: A method includes receiving an activation signal at a semiconductor device and generating an output power signal at the semiconductor device in response to receiving the activation signal. The output power signal has a duty cycle. The method also includes providing the output power signal to a load. The output power signal provides power to the load. An amount of power provided to the load is based on the duty cycle of the output power signal. In addition, the method includes adjusting the duty cycle of the output power signal using at least one of a current limiter and a power limiter integrated in the semiconductor device. ...


- Carrollton, TX, US
Inventors: Gary J. Burlak, Marian Mirowski
USPTO Applicaton #: #20070013361

The Patent Description & Claims data below is from USPTO Patent Application 20070013361, Semiconductor device having an integrated, self-regulated pwm current and power limiter and method.

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stats Patent Info
Application #
US 20070013361 A1
Publish Date
01/18/2007
Document #
File Date
12/31/1969
USPTO Class
Other USPTO Classes
International Class
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Drawings
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20070118|20070013361|semiconductor device having an integrated, self-regulated pwm current and power limiter and method|A method includes receiving an activation signal at a semiconductor device and generating an output power signal at the semiconductor device in response to receiving the activation signal. The output power signal has a duty cycle. The method also includes providing the output power signal to a load. The output |
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