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  Semiconductor device having a well structure for improving soft error rate immunity and latch-up immunity and a method of making such a deviceUSPTO Application #: 20080026524Title: Semiconductor device having a well structure for improving soft error rate immunity and latch-up immunity and a method of making such a device Abstract: A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain of first conductivity type are formed in the second well, and second conductivity type MOSFETs including source/drain of second conductivity type in the first well. A third well of second conductivity type is formed at a region under the first wells and the drain of the second conductivity type MOSFETs. The first well is connected to the semiconductor substrate between the first well and the third well. (end of abstract) Agent: Marger Johnson & Mccollom, P.C. - Portland, OR, US Inventor: Hyuck-Chai Jung USPTO Applicaton #: 20080026524 - Class: 438232000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Complementary Insulated Gate Field Effect Transistors (i.e., Cmos), Self-aligned, Plural Doping Steps The Patent Description & Claims data below is from USPTO Patent Application 20080026524. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This is a Divisional of U.S. patent application Ser. No. 10/961,927, filed Oct. 8, 2004, now pending, which claims priority under 35 U.S.C. .sctn. 119 of Korean Patent Application No. 2003-70310, filed Oct. 9, 2003. The entire contents of which are hereby incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of this Invention [0003] This invention relates to semiconductor memory devices and to methods of fabricating semiconductor memory devices. More particularly, the present invention relates to semiconductor memory devices that have a well structure for improving soft error rate immunity and latch-up immunity and to a method of fabricating such devices. [0004] 2. Description of Prior Art [0005] Complementary metal oxide semiconductor devices (CMOS devices) have excellent power dissipation, noise margin and reliability characteristics, and they are widely used in many semiconductor products including memories, microprocessors and application specific integrated circuits (ASICs). [0006] CMOS devices may not only be used in memory cell regions but they may also be used in peripheral circuit regions of static RAMs (SRAMs). SRAMs that use CMOS devices have small standby current requirements and high data retention. The unit cell of an SRAM generally includes two driver transistors, two access transistors and two load transistors. The driver and access transistors in an SRAM cell can be NMOSFETs and the load transistors can be PMOSFETs. Such unit cells, called "a full CMOS cells," require only a small standby current and they have a large noise margin. They are therefore widely used in high-performance SRAMs that have a low power supply voltage. [0007] CMOS devices such as CMOS inverters may sometimes suffer from problems such as soft errors and latch-up. A soft error is a process in which an electron-hole pair (EHP) generated in the semiconductor substrate by alpha particles or cosmic ray, destroys information stored in the memory cell. This loss of information occurs when electric charges in specific nodes (e.g., a lower electrode of the capacitor in the DRAM or a drain of the driver transistor in the SRAM) exceed a critical quantity. Even if a semiconductor device is highly integrated, the capacitor in a DRAM must have a relatively high capacitance. As a result, soft errors in DARMs do not present a significant problem in highly integrated DARMs. However, since SRAMs do not use a capacitor as the memory cell for storing information, reduction of capacitance accompanies high integration. Consequently, as the integration of SRAMs is increased, a technique for improving the soft error rate immunity is highly desired. [0008] One conventional technique for improving the soft error rate immunity is disclosed in U.S. Pat. No. 5,877,051. Such a prior art technique is illustrated in FIG. 1 which is a schematic cross-sectional view of a semiconductor device. [0009] As shown in FIG. 1, a plurality of N-wells 20n and P-wells 20p are disposed in predetermined regions of the semiconductor substrate 10. A plurality of PMOSFETs are formed at the N-well 20n, and a plurality of NMOSFETs are formed at the P-well 20p. The NMOSFETs and the PMOSFETs include a gate insulation layer 50 and gate electrodes 30. The gate insulation layer 50 is formed on the active region defined by the device isolation layer 15 and the gate electrodes 30 are formed on the gate insulation layer 50. In addition, the NMOSFETs include N-type impurity regions 40n formed in the P-well 20p, and the PMOSFETs include P-type impurity region 40p formed in the N-well 20n. These NMOSFETs and PMOSFETs can be connected with predetermined interconnections (not shown) to form a CMOS inverter, a flip-flop circuit, a CMOS SRAM cell or the like. [0010] In a conventional method of improving the soft error rate immunity, a deep N-well 60n is formed under the P-well 20p. The deep N-well 60n plays a role in reducing the generation EHPs by shortening the funneling length of high energy particles. In addition, the deep N-well 60n collects a part of the charges generated by high energy particles to decrease the electric charges accumulated in a node of the inverter. However, the deep N-well 60n may deteriorate the latch-up immunity. [0011] Latch-up is an important technical problem in CMOS devices. Latch-up is described in various textbooks. For example, see "Device Electronics for Integrated Circuits", pp. 458-456, by Richard S. Muller and Theodore I. Kamins. Latch-up results from the structure of parasitic thyristor formed by the NMOSFETs and PMOSFETs. As described by Muller, susceptibility to latch-up may be decreased by reducing well resistance. This reduction in well resistance enables the electrons to be discharged fast, so as to prevent an abnormal variation of the well potential. Latch-up may be particularly serious in case of holes rather than electrons because of the difference in mobility. Therefore, the art of reducing the latch-up susceptibility is generally focused on reducing the electric resistance of the P-well 20p. [0012] FIG. 2 is a cross-sectional view for illustrating a prior art method of reducing the P-well resistance. FIGS. 3A and 3B are resistor circuit diagrams for illustrating schematically electric resistances of the P-wells in FIGS. 1 and 2, respectively. [0013] First, as shown in FIG. 1, the bottom surface and the sidewall of the P-well 20p are surrounded by N-type wells 20n and 60n. This configuration corresponds to a long-line shaped resistor structure shown in FIG. 3A. The resistance of the P-well 20p is determined by distances between conductive structures (e.g., well strappings) that are connected to the P-well 20p in the state of forward bias. The integration density of the conductive structures connected to the P-well 20p should be increased to decrease the well resistance. However, this method for increasing a density of the well pick-up is undesirable because it may degrade integration density of the semiconductor devices. [0014] As illustrated in FIG. 2, the well structure may be formed without forming the deep N-well 60n. In this case the N-type wells 20n and 60n do not surround the P-well 20p. As illustrated in FIG. 3B, the well structure corresponds to a resistor structure that wells are connected in parallel. This parallel connection structure of resistor reduces the resistance of the P-well 20p, and the latch up susceptibility can be decreased. However, the well structure without the deep N-well 60n formed under the P-well 20p results in reducing the soft error immunity. SUMMARY OF THE INVENTION [0015] The present invention provides a CMOS device that has improved soft error and latch up immunities. [0016] A CMOS device according to the present invention includes first wells of first conductivity type and second wells of second conductivity type formed in a semiconductor substrate of first conductivity type. A first conductivity type MOSFETs including a source and drain of first conductivity type are formed in the second well. A second conductivity type MOSFETs including a source and drain of a second conductivity type are formed in the first well. A third well of a second conductivity type disposed under both the first wells and the drain of the second conductivity type MOSFETs. [0017] The first wells can be connected to the semiconductor substrate between the third wells. A fourth well of first conductivity type can be disposed in the semiconductor substrate under and between the third wells, and the first wells can be connected to the fourth well between the third wells. The third well can be connected to a bottom of the second well. The third well can be formed under the entire region of the second well. [0018] The first conductivity type MOSFETs can form the load transistors of an SRAM, and the second conductivity type MOSFETs can form the driver transistors and the transfer transistors of an SRAM. BRIEF DESCRIPTION OF THE DRAWINGS [0019] FIG. 1 is a cross-sectional view illustrating a well structure of CMOS device according to one embodiment of the prior art. [0020] FIG. 2 is a cross-sectional view illustrating a well structure of CMOS device according to another embodiment of the prior art. Continue reading... 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