| Semiconductor device equipped with a voltage step-up circuit -> Monitor Keywords |
|
|
  Semiconductor device equipped with a voltage step-up circuitUSPTO Application #: 20070122964Title: Semiconductor device equipped with a voltage step-up circuit Abstract: A semiconductor device is equipped with a step-up circuit having a series of multiple charge pump units. Each of the units has a well separation type MOS transistor. The separation well of the transistor is coupled to a high potential so as to form double reverse biases between the N-type well and a P-type substrate and between the N-type well and a P-type well. This permits the threshold Vth of the MOS transistor to be held at low level. The units are provided with a clock whose current supply capability is limited until a predetermined condition (that a predetermined period of time has elapsed after the onset of the step-up circuit by a startup signal or that the output voltage has reached a predetermined level). This limitation of the clock facilitates suppression of power consumption by the step-up circuit during a startup, thereby reducing changes in amplitude of a supply voltage. (end of abstract) Agent: Hogan & Hartson L.L.P. - Los Angeles, CA, US Inventors: Michio NAKAGAWA, Kazuo SATO, Hiromi UENOYAMA, Yasuyuki OHNISHI, Kazunori TORII USPTO Applicaton #: 20070122964 - Class: 438202000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Complementary Insulated Gate Field Effect Transistors (i.e., Cmos), And Additional Electrical Device, Including Bipolar Transistor (i.e., Bicmos) The Patent Description & Claims data below is from USPTO Patent Application 20070122964. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The invention relates to a semiconductor device equipped with a voltage step-up circuit for stepping up a low supply voltage to higher voltages BACKGROUND OF THE INVENTION [0002] Step-up circuits have been widely used in conventional semiconductor devices (referred to as ICs) such as EEPROM or flash memories in order to provide them with suitable power from a standardized single power source within the IC. [0003] FIG. 1 is a schematic diagram of a conventional step-up circuit. The step-up circuit of FIG. 1 has a series of N-stage charge pump units U1-Un (referred to as units), with U1 being the first stage receiving a supply voltage and Un being the final output unit. The unit U1 of the first stage is supplied with a supply voltage Vcc (which is for example 2 V or 3 V) via a diode-connected N-type MOS (referred to as NMOS) transistor QO. The output voltage of the unit Un is stored in a capacitor Co connected to the unit Un. This voltage (typically 10 V) is the output voltage Vout of the circuit. [0004] Each of the units U1-Un has a similar structure, and only the unit U1 will be discussed. The unit U1 includes an NMOS transistor Q1 and a capacitor C1. The source S of the NMOS transistor Q1 is connected to the gate G thereof, thereby forming a so-called diode connection. The source S is also connected to the supply voltage Vcc via the NMOS transistor Q0. The drain D of the NMOS transistor Q1 is connected to the unit U2 of the next stage [0005] The capacitor C1 has one end connected to the source S of the NMOS transistor Q1 and the other end connected to a clock line of a first clock CLK1. The capacitors of odd numbered units U1, U3, . . . are connected to the clock line of the first clock CLK1, while the capacitors of even numbered units U2, U4, . . . are connected to a clock line of a second clock CLK2. [0006] The clocks CLK1 and CLK2 constitute a two-phase clock having two opposite phases. The two phases have the same voltage amplitude which equals to, for example, the supply voltage Vcc. [0007] In the step-up circuit shown in FIG. 1, when clocked by the clocks CLK1 and CLK2, capacitors of the respective units are charged up in turn to the supply voltage Vcc, creating the step-up voltage Vout. The resultant output voltage Vout may be supplied to an EEPROM for example. [0008] The drain D and source S of the NMOS transistor of each unit are formed on a P-type substrate, which is grounded. The gate G of the NMOS is directly connected to the source S. In actuality, however, a threshold voltage Vth exists between the gate G and the drain D, so that the drain potential of respective units is lower than that of the source S by the threshold voltage Vth. That is, the voltage stepped up by respective units will be at most [Vcc-Vth]. [0009] It is noted that the threshold voltage Vth of respective NMOS transistors increases with the potential difference between the source and the substrate potentials (the substrate normally grounded) due to the substrate bias effect. Consequently, a step-up voltage of a unit decreases from the first to the final stages. [0010] For this reason, in order to obtain an appreciably high output voltage from a given supply voltage Vcc, it is necessary to implement many charge pump units connected in series. If the threshold voltage Vth is higher than the supply voltage Vcc, stepping up of voltage itself is not possible. [0011] This problem is serious especially when the supply voltage Vcc is low. Therefore, there is a need to solve this problem for modern IC devices designed to be operable at a greatly reduced supply voltage. [0012] A further problem pertinent to a step-up circuit concerns minimization of the circuit. Normally, the insulation layer serving as a dielectric of the capacitor used in a charge pump circuit is relatively thick to withstand a required stepped up voltage. However, since the capacitance of the capacitor decreases with the thickness of the insulation layer, the capacitor requires a larger area. [0013] In order to reduce the areas of capacitors, thereby reducing the areas of the charge pump circuits, Japanese Patent Application Laid Open H5-28786 proposes an arrangement in which the insulation layers of low-voltage capacitors near the input end of the charge pump circuit have a reduced thickness while those of the capacitors near the terminal end of the charge pump circuit have an increased thickness to withstand a high stepped up voltage. [0014] In this step-up circuit, however, the insulation layers are relatively thick near the terminal end of the circuit, which prevents reduction of the capacitor area, and in some cases could result in an increase of the capacitor area on a chip. [0015] In addition, in the step-up circuit as shown in FIG. 1, capacitors C1-Cn of the respective units U1-Un have a relatively large capacitance so as to be able to provide a large current along with a required output voltage Vout. Thus, during a startup when all the units U1-Un begin to operate at substantially the same time, drawing a large current from the voltage supply, they cause a large voltage drop and instability in the supply voltage. This instability takes place every time the step-up circuit is started up and can cause errors in the operations (e.g. write and read) of a logic circuit, for example, of a semiconductor device equipped with a step-up circuit. [0016] It is possible to avoid such instability by proving the power supply with a sufficiently large power to cope with a large current requirement at all times. However, it is impractical to do so with, for example, light-weight and/or miniaturized semiconductor devices for use in portable apparatuses. SUMMARY OF THE INVENTION [0017] It is, therefore, an object of the invention to provide a semiconductor device equipped with a step-up circuit having a minimum number of charge pump units yet capable of providing a required high output voltage by totally or substantially removing the limitation by the threshold voltages of the MOS transistors used. [0018] To attain the object above, the invention utilizes different capacitors in early stages and final stages of the multi-staged charge pump circuit. Thus, all the capacitors of the charge pump circuit of the semiconductor device occupy only reduced chip areas near not only the first stage but also the terminal stage of the charge pump circuit area. [0019] The step-up circuit of the invention is adapted to change step-up conditions to minimize power consumption during a startup. Thus, the inventive semiconductor device equipped with such step-up circuit exhibits only a limited adverse effects caused by the voltage change on other circuits during a startup. [0020] In accordance with one aspect of the invention, there is provided a semiconductor device equipped with a voltage step-up circuit, said voltage step-up circuit comprising multiple charge pump units connected in series, each charge pump unit consisting of a MOS transistor and a capacitor having one end connected to the input or output end of said MOS transistor and another end connected to a clock line supplying a clock, said multiple charge pump units adapted to step up a supply voltage in response to said clock, wherein [0021] said MOS transistor is a well separation type MOS transistor having [0022] a second-conduction type well formed in a first-conduction type substrate; [0023] a first-conduction type well formed in said second-conduction type well; [0024] a second-conduction type source region formed in said first-conduction type well; [0025] a second-conduction type drain region away from said source region and separated by a channel region; and [0026] a gate formed above, and separated by an insulation layer from, said channel region, and wherein Continue reading... Full patent description for Semiconductor device equipped with a voltage step-up circuit Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Semiconductor device equipped with a voltage step-up circuit patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Semiconductor device equipped with a voltage step-up circuit or other areas of interest. ### Previous Patent Application: Latch-up prevention in semiconductor circuits Next Patent Application: Stress engineering using dual pad nitride with selective soi device architecture Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Semiconductor device equipped with a voltage step-up circuit patent info. IP-related news and info Results in 0.21458 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
||
