| Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility -> Monitor Keywords |
|
|
  Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobilityUSPTO Application #: 20060208250Title: Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility Abstract: The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate electrodes and strained Si source/drain regions of P-channel or N-channel transistors, respectively. (end of abstract) Agent: Mcdermott Will & Emery LLP - Washington, DC, US Inventors: Sey-Ping Sun, David E. Brown USPTO Applicaton #: 20060208250 - Class: 257019000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Thin Active Physical Layer Which Is (1) An Active Potential Well Layer Thin Enough To Establish Discrete Quantum Energy Levels Or (2) An Active Barrier Layer Thin Enough To Permit Quantum Mechanical Tunneling Or (3) An Active Layer Thin Enough To Permit Carrier Transmission With Substantially No Scattering (e.g., Superlattice Quantum Well, Or Ballistic Transport Device), Heterojunction, Quantum Well, Superlattice, Strained Layer Superlattice, Si X Ge 1-x The Patent Description & Claims data below is from USPTO Patent Application 20060208250. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to micro-miniaturized semiconductor devices comprising transistors on silicon-germanium. The present invention is particularly applicable in fabricating transistors with enhanced channel carrier mobility. BACKGROUND OF THE INVENTION [0002] The relentless pursuit of miniaturized high speed semiconductor devices continues to challenge the limitations of conventional semiconductor materials and fabrication techniques. Conventional semiconductor devices typically comprise a plurality of active devices in or on a common semiconductor substrate, e.g., CMOS devices comprising at least a pair of PMOS and NMOS transistors in spaced adjacency. Current technology utilizes crystalline semiconductor wafers as substrates, such as a lightly p-doped epitaxial ("epi") layer of silicon (Si) grown on a heavily-doped, crystalline Si Substrate. The low resistance of the heavily-doped substrate is necessary for minimizing susceptibility to latch-up, whereas the light doping of the epi layer permits independent tailoring of the doping profiles of both the p-type and n-type wells formed therein as part of the fabrication sequence, thereby resulting in optimal PMOS and NMOS transistor performance. [0003] The use of the very thin epi layers, i.e., several .mu.m thick, is made possible by utilizing shallow trench isolation ("STI"), which advantageously minimizes up-diffusion of p-type dopant(s) from the more heavily-doped substrate into the lightly-doped epi layer. In addition, STI allows for closer spacing of adjacent active areas by avoiding the "bird's beak" formed at the edge of each LOCOS isolation structure. STI also provides better isolation by creating a more abrupt structure, reduces the vertical step from active area to isolation to improve gate lithography control, eliminates the high temperature field oxidation step that can cause problems with large diameter, i.e., 8 inch, wafers, and is scalable to future logic technology generations. [0004] Substrates based on "strained silicon" have attracted interest as a semiconductor material which provides increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. A very thin, tensilely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition of silicon-germanium (Si--Ge) buffer layer several microns thick, which Si--Ge buffer layer in turn is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. The Si--Ge buffer layer typically contains 12 to 25 at. % Ge. Strained Si technology is based upon the tendency of the Si atoms, when deposited on the Si--Ge buffer layer, to align with the greater lattice constant (spacing) of Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on a substrate (Si--Ge) comprised of atoms which are spaced further apart, they "stretch" to align with the underlying Si and Ge atoms, thereby "stretching" or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size. Conventional practices based on strained silicon technology also involve epitaxially growing a relaxed silicon layer on a tensilely stressed silicon layer which is subsequently doped to form relaxed source/drain regions in the relaxed silicon layer. [0005] The mobility of electrons is faster than the mobility of holes in conventional bulk silicon substrates. Accordingly, in conventional CMOS transistors, the drive current of the PMOS transistor is less than the drive current of the NMOS transistor creating an imbalance. This imbalance is exacerbated in CMOS transistors fabricated on or within a tensilely stressed active device area formed in a strained lattice semiconductor substrate, e.g., strained Si on Si--Ge, because the increase in electron mobility is greater than the increase in hole mobility. [0006] As micro-miniaturization proceeds, there is an attendant need to increase the drive current of transistors, including transistors formed on various types of strained Si--Ge substrates, by enhancing carrier mobility. Accordingly, there exists a need for methodology enabling the fabrication of semiconductor devices comprising transistors formed on Si--Ge substrates with enhanced drive currents by increasing channel carrier mobility and the resulting semiconductor devices. DISCLOSURE OF THE INVENTION [0007] An advantage of the present invention is a method of fabricating a semiconductor device comprising transistors on Si--Ge substrates with enhanced drive currents. [0008] Another advantage of the present invention is a semiconductor device comprising transistors based on Si--Ge substrates with enhanced drive currents. [0009] Additional advantages and other aspects and features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims. [0010] According to the present invention, the foregoing and other advantages are obtained in part by a semiconductor device comprising: a substrate comprising a layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (Si--Ge); a transistor comprising source/drain regions and a gate electrode over the substrate with a gate dielectric layer therebetween; and a stressed dielectric liner over side surfaces of the gate electrode and over the source/drain regions. [0011] Another advantage of the present invention is a method of manufacturing a semiconductor device, the method comprising: forming a substrate comprising a layer of silicon (Si) having a strained lattice on a layer of silicon-germanium (Si--Ge); forming a transistor comprising source/drain regions and a gate electrode, having an upper surface and side surfaces, over the substrate with gate dielectric layer therebetween; and forming a stressed dielectric liner over the side surfaces of the gate electrode and over the source/drain regions. [0012] Embodiments of the present invention comprise forming dielectric sidewall spacers on side surfaces of the gate electrode, such as an oxide liner and a nitride layer thereon, epitaxially growing a relaxed Si layer on the strained Si layer, forming source/drain regions in the relaxed Si layer and then depositing the stressed dielectric liner on the sidewall spacers, on the relaxed source/drain regions and on a portion of the strained Si layer between the sidewall spacers and raised source/drain regions. [0013] Embodiments of the present invention also include forming dielectric sidewall spacers on side surfaces of the gate electrode, forming source/drain regions in the strained Si layer, forming a metal silicide layer on the upper surface of the gate electrode and a metal silicide layer on the source/drain regions, removing the dielectric sidewall spacers to expose a portion of the strained Si layer adjacent the side surfaces of the gate electrode, and then forming the stress dielectric liner on the metal silicide layer, on the upper surface of the gate electrode, on the side surfaces of the gate electrode, on the adjacent exposed portions of the strained Si layer, and on the silicide layer overlying the source/drain regions. [0014] In embodiments of the present invention comprising N-channel transistors, the stressed dielectric liner exhibits high tensile stress. In embodiments of the present invention comprising P-channel transistors, the stressed dielectric liner exhibits high compressive stress. The stressed dielectric liner may comprise a layer of silicon nitride, silicon carbide or silicon oxynitride, at a thickness of about 200 .ANG. to about 1000 .ANG.. [0015] Embodiments of the present invention include fabricating semiconductor devices comprising complimentary MOS (CMOS) transistors, with a compressive film on the PMOS transistor and a tensile film on the NMOS transistor. According to one aspect of this invention, process flow includes depositing a compressive stressed nitride film over both the NMOS and PMOS transistors, and then depositing a thin buffer film, such as an oxide or oxynitride film, over both the NMOS and PMOS transistors. Selective etching is then conducted to remove the oxide and compressive stressed nitride films from the NMOS transistor while masking the PMOS transistor. A tensile stressed nitride film is then deposited over both the NMOS and PMOS transistors, and then selectively etched away from the PMOS transistor. The resulting CMOS device comprises an NMOS transistor with a tensile stressed film thereon and a PMOS transistor with a compressive stress film thereon. [0016] Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative. BRIEF DESCRIPTION OF THE DRAWINGS [0017] FIGS. 1 and 2 schematically illustrate sequential phases of a method in accordance with an embodiment of the present invention. [0018] FIGS. 3 through 6 schematically illustrate sequential phases of a method in accordance with another embodiment of the present invention. [0019] FIGS. 7 through 14 schematically illustrate sequential phases of a method in accordance with another embodiment of the present invention. [0020] In FIGS. 1 and 2, similar features or elements are denoted by similar reference characters; in FIGS. 3 through 6, similar features or elements are denoted by similar reference characters; and in FIGS. 7 through 14, similar features or elements are denoted by similar reference characters. Continue reading... Full patent description for Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility or other areas of interest. ### Previous Patent Application: Programmable conductor memory cell structure and method therefor Next Patent Application: Molecular rectifiers Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Semiconductor device based on si-ge with high stress liner for enhanced channel carrier mobility patent info. IP-related news and info Results in 0.54133 seconds Other interesting Feshpatents.com categories: Software: Finance , AI , Databases , Development , Document , Navigation , Error |
||
