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10/23/08 - USPTO Class 438 |  65 views | #20080261370 | Prev - Next | About this Page  438 rss/xml feed  monitor keywords

Semiconductor device and method of fabricating the same

USPTO Application #: 20080261370
Title: Semiconductor device and method of fabricating the same
Abstract: forming a second conductive layer on the second insulating film. annealing the second insulating film in a second processing chamber; and performing a modification process on the second insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside; forming a second insulating film on the first conductive layer in a first processing chamber isolated from an outside; forming a first conductive layer on the first insulating film; forming a first insulating film on a semiconductor substrate; According to the present invention, there is provided a semiconductor device fabrication method comprising: (end of abstract)



USPTO Applicaton #: 20080261370 - Class: 438303 (USPTO)

Semiconductor device and method of fabricating the same description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20080261370, Semiconductor device and method of fabricating the same.

Brief Patent Description - Full Patent Description - Patent Application Claims
  monitor keywords CROSS REFERENCE TO RELATED APPLICATION

This application is based upon and claims benefit of priority under 35 USC §119 from the Japanese Patent Application No. 2005-15415, filed on Jan. 24, 2005, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method of fabricating the same.

Conventionally, a NAND flash memory has been developed as a nonvolatile semiconductor memory. A memory cell transistor of this NAND flash memory has a structure in which a floating gate electrode formed on a semiconductor substrate via a tunnel insulating film and a control gate electrode formed on this floating gate electrode via an inter-electrode insulating film are stacked.

Recently, to decrease the cell size, a method of using an alumina (Al2O3) film, instead of the conventional ONO film (a stacked film in which a silicon oxide film, silicon nitride film, and silicon oxide film are stacked), as an inter-electrode insulating film is proposed (reference 1).

Since the alumina (Al2O3) film is a high-dielectric-constant film having a relative dielectric constant higher than that of the ONO film, the area of the inter-electrode insulating film can be reduced. As a consequence, the cell size can be decreased.

The NAND flash memory stores “1” data in the memory cell transistor by discharging electrons from the floating gate electrode to the semiconductor substrate, and stores “0” data in the memory cell transistor by injecting electrons into the floating gate electrode from the semiconductor substrate.

Unfortunately, the density of a high-dielectric-constant film is low. Therefore, if a high-dielectric-constant film is used as the inter-electrode insulating film, electrons injected into the floating gate electrode from the semiconductor substrate by applying an electric field of a predetermined level between the control gate electrode and semiconductor substrate penetrate through the inter-electrode insulating film. This increases a leakage current flowing through the control gate electrode.

To prevent this, therefore, it is necessary to suppress the leakage current by performing a predetermined heating process (annealing) for a high-dielectric-constant film deposited on a conductive layer serving as the floating gate electrode, thereby modifying the high-dielectric-constant film.

The reference concerning the use of the alumina (Al2O3) film as the inter-electrode insulating film is as follows. Reference 1: Symposium on VLSI Technology Digest of Technical Papers, p. 117, 1997

SUMMARY OF THE INVENTION

According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising:

forming a first insulating film on a semiconductor substrate;

forming a first conductive layer on the first insulating film;

forming a second insulating film on the first conductive layer in a first processing chamber isolated from an outside;

performing a modification process on the second insulating film in the first processing chamber, and unloading the semiconductor substrate from the first processing chamber to the outside;

annealing the second insulating film in a second processing chamber; and

forming a second conductive layer on the second insulating film.



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Patent Applications in related categories:

20090286375 - Method of forming sidewall spacers to reduce formation of recesses in the substrate and increase dopant retention in a semiconductor device - A method of forming sidewall spacers for a gate in a semiconductor device includes re-oxidizing/annealing silicon of the substrate and silicon of the gate after formation of the gate. The substrate is re-oxidized by performing an anneal in an inert atmosphere or ambient. The substrate may be re-oxidized/annealing after depositing ...


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