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04/13/06 - USPTO Class 438 |  134 views | #20060079023 | Prev - Next | About this Page  438 rss/xml feed  monitor keywords

Semiconductor device and manufacturing method for the same

USPTO Application #: 20060079023
Title: Semiconductor device and manufacturing method for the same
Abstract: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip. Therefore, it becomes possible to prevent the occurrence of microcracks in the second semiconductor chip and to prevent the occurrence of defective fine metal wire connections caused by the impact at the time of electrical connection of the second semiconductor chip to the wiring board. (end of abstract)



Agent: Stevens, Davis, Miller & Mosher, LLP - Washington, DC, US
Inventors: Toshiyuki Fukuda, Hiroaki Fujimoto, Mutsuo Tsuji, Takashi Yui, Yoshiaki Takeoka
USPTO Applicaton #: 20060079023 - Class: 438109000 (USPTO)

Related Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor, Assembly Of Plural Semiconductive Substrates Each Possessing Electrical Device, Stacked Array (e.g., Rectifier, Etc.)

Semiconductor device and manufacturing method for the same description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20060079023, Semiconductor device and manufacturing method for the same.

Brief Patent Description - Full Patent Description - Patent Application Claims
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[0001] This is a divisional application of application Ser. No. 10/636,595 filed Aug. 8, 2003.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device molded in resin wherein a plurality of semiconductor chips and passive parts are mounted within one semiconductor device molded in resin and to a manufacturing method for the same. The present invention relates, in particular, to a semiconductor device molded in resin wherein two semiconductor chips are stacked and mounted on a wiring board and to a manufacturing method for the same.

[0004] 2. Description of the Background Art

[0005] In recent years reduction in the weight and thickness of mobile apparatuses, as represented by notebook personal computers, cellular phones, and the like, has rapidly progressed. According to such a trend an increase in the density of electronic parts and an enhancement in performance are required for electronic parts mounted on the mother boards of the apparatuses, in particular, for semiconductor devices, which make up the core of the apparatuses. Conventionally an MCM (multichip module) wherein a plurality of semiconductor chips is mounted on a plane surface of an interposer (substrate having external terminals for direct mounting on a mother board), for example, is generally used (see Japanese unexamined patent publication H09 (1997)-8220 (FIG. 1)) in the case wherein a plurality of semiconductor chips is incorporated within one semiconductor device. Moreover, in order to further increase the configuration density within the semiconductor device, a method of stacking semiconductor chips, for example, has come into wide use (see Japanese unexamined patent publication H11 (1999)-204720 (FIGS. 1 and 3)). The size of a semiconductor chip mounted above the lower chip is, in general, smaller than the lower chip to make connection of fine metal wires easy in the case wherein a plurality of semiconductor chips is stacked in a conventional manner. In some cases, however, the dimensions of the upper semiconductor chip are greater than that of the lower chip in the configuration wherein the lower chip is, for example, directly bonded to a board and the upper semiconductor chip is mounted on the lower chip so that the electric circuit thereof faces upward (see Japanese unexamined patent publication 2000-299431 (FIG. 1) and Japanese unexamined patent publication 2001-320014 (FIG. 1)). These cases disclose a technique of supporting the upper chip with supports, or support members.

[0006] The upper semiconductor chip is larger than the lower semiconductor chip and the upper semiconductor chip is in a condition extending in an overhanging manner over the lower semiconductor chip, which is a flip chip, in a conventional semiconductor device molded in resin having a configuration wherein the lower semiconductor chip is directly flip chip bonded to a carrier board and the upper semiconductor chip is mounted on the lower chip with the electric circuit thereof facing upward. In this case microcracks may occur in the upper semiconductor chip or defective connections of fine metal wires may occur due to impact at the time of connection of fine metal wires to the upper semiconductor chip by means of an ultrasonic wave or thermocompression bonding method.

[0007] Here, a problem is described in reference to FIGS. 10A and 10B. FIG. 10A is a cross sectional view showing a conventional semiconductor device molded in resin and FIG. 10B shows an enlarged view of a portion of FIG. 10A. In addition, the enlarged view shows the phenomenon that is the problem. In a semiconductor device molded in resin having a configuration wherein first semiconductor chip 1, is directly flip chip bonded to a carrier board 20 and a second semiconductor chip 2 is mounted on first semiconductor chip 1 so that the electric circuit thereof faces upward, Au wires 7 are connected to electrode pads 4 of second semiconductor chip 2 using capillary 10, as shown in FIGS. 10A and 10B. At this time second semiconductor chip 2 bends symbol (11 indicates the amount of bending .DELTA.h) due to the impact from the load when ball bonding is carried out while ultrasonic waves and the load are being applied to an electrode pad 4 at a high temperature (from 150.degree. C. to 250.degree. C.) in the case wherein second semiconductor chip 2 is significantly larger than first semiconductor chip 1. Therefore, a microscopic crack 12 occurs in the case wherein an Au wire 7 cannot be stably bonded or in the case wherein the load is too great. Stud bumps are denoted by symbol 5, conductive paste is denoted by symbol 6, underfill resin is denoted by symbol 13 and adhesive is denoted by symbol 14 in FIGS. 10A and 10B.

SUMMARY OF THE INVENTION

[0008] A purpose of the present invention is to provide a semiconductor device and a manufacturing method for the same wherein the reliability of connections of fine metal wires connecting an upper semiconductor chip to a wiring board can be improved in the case wherein the upper semiconductor chip, which is located above a lower semiconductor chip, is significantly larger than the lower semiconductor chip in a configuration wherein the two semiconductor chips are stacked and mounted on a wiring board.

[0009] In order to achieve the above described purpose, a semiconductor device of the first invention is provided with: a wiring board having a first wiring electrode and a second wiring electrode; a first semiconductor chip having, on the top surface, an electrode connected to the first wiring electrode; and a second semiconductor chip, which is mounted on the first semiconductor chip, which is larger than the first semiconductor chip and which has, at least in the periphery of the top surface, an electrode electrically connected to the second wiring electrode by means of a fine metal wire, wherein the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the sides of the adhesive are inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the sides of the first semiconductor chip.

[0010] According to this configuration the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the sides of the first semiconductor chip and, therefore, the size and form of the the adhesive can be optimized. Therefore, it becomes possible to prevent the occurrence of microcracks in the second semiconductor chip and to prevent the occurrence of defective fine metal wire connections caused by the impact at the time of electrical connection of the second semiconductor chip to the wiring board. Thereby, a semiconductor device of a high reliability molded in resin wherein semiconductor chips are stacked can be provided.

[0011] A semiconductor device of the second invention is the semiconductor device of the first invention wherein the area of the cross section of the adhesive in a plane along the plane direction of the first semiconductor chip is no less than the area of the rear surface of the first semiconductor chip. According to this configuration the area of the cross section of the adhesive in a plane along the plane direction of the first semiconductor chip is no less than the area of the rear surface of the first semiconductor chip and, therefore, an adhesive having a size that is significantly greater than that of the first semiconductor chip and a sufficient thickness can be formed on the rear surface of the second semiconductor chip. Thereby, defective bonding caused by the impact to the fine metal wires and microcracks in the second semiconductor chip can be further prevented.

[0012] A semiconductor device of the third invention is the semiconductor device of the first invention wherein the surface of the side of the adhesive is in a concave, curved form. According to this configuration the surface of the side of the adhesive is in a concave, curved form and, therefore, a cross section of the adhesive perpendicular to the rear surface of the first semiconductor chip is in an inverted arched form, wherein sufficient stiffness for bearing mechanical stress is provided in the same manner as in a bridge pier so as to be able to bear the load from wire bonding.

[0013] A semiconductor device of the fourth invention is the semiconductor device of the first invention wherein the adhesive is formed over the entire region of the rear surface and over a portion of the sides of the first semiconductor chip. According to this configuration the adhesive is formed over the entire region of the rear surface and over a portion of the sides of the first semiconductor chip and, therefore, the application of a bending moment force with a starting point at the corner portion of the rear surface of the first semiconductor chip can be suppressed in the case wherein the load from wiring bonding is applied to the electrode of the second semiconductor chip.

[0014] A semiconductor device of the fifth invention is the semiconductor device of the first invention wherein an underfill resin is placed between the wiring board and the first semiconductor chip and wherein at least a portion of the side of the underfill resin is covered with an adhesive. According to this configuration an underfill resin is placed between the wiring board and the first semiconductor chip and at least a portion of the side of the underfill resin is covered with an adhesive and, therefore, the application of a bending moment force with a starting point at the corner portion of the rear surface of the first semiconductor chip can be further suppressed.

[0015] A semiconductor device of the sixth invention is the semiconductor device of the first invention wherein a passive part is electrically connected to the mounting surface of the first semiconductor chip on the wiring board, wherein the second semiconductor chip is larger than the region where the first semiconductor chip and the passive part are placed and wherein the rear surface of the second semiconductor chip and the rear surface of the passive part facing the rear surface of the second semiconductor chip are adhered to each other. According to this configuration a passive part is electrically connected to the mounting surface of the first semiconductor chip on the wiring board, wherein the second semiconductor chip is larger than the region where the first semiconductor chip and the passive part are placed and wherein the rear surface of the second semiconductor chip and the rear surface of the passive part facing the rear surface of the second semiconductor chip are adhered to each other and, therefore, the same working effects as of the first invention can be gained in a semiconductor device wherein a plurality of semiconductor chips and a passive part are mounted.

[0016] A semiconductor device of the seventh invention is the semiconductor device of the first invention wherein a passive part is electrically connected to the mounting surface of the first semiconductor chip on the wiring board, wherein the second semiconductor chip is larger than the region where the first semiconductor chip and the passive part are placed, wherein a spacer is adhered to the rear surface of the passive part so that the height of the spacer becomes approximately equal to the height of the rear surface of the first semiconductor chip and wherein the rear surface of the second semiconductor chip and the rear surface of the passive part facing the rear surface of the second semiconductor chip are adhered to each other in the condition wherein the spacer is intervened therebetween. According to this configuration a spacer is adhered to the rear surface of a passive part so that the height of the spacer becomes approximately equal to the height of the rear surface of the first semiconductor chip and, therefore, the second semiconductor chip is maintained in a stable condition even in the case wherein the height of the rear surface of the first semiconductor chip and the height of the rear surface of the passive part differ from each other and the load from wire bonding is applied to the electrode of the second semiconductor chip.

[0017] A manufacturing method for a semiconductor device of the eighth invention is provided with: the step of preparing a wiring board having a first wiring electrode and a second wiring electrode as well as a first semiconductor chip having an electrode on the top surface; the step of electrically connecting the first wiring electrode of the wiring board to the electrode of the first semiconductor chip via a bump; the step of preparing a second semiconductor chip that is larger than the first semiconductor chip and that has an electrode in at least the periphery of the top surface; the step of adhering the rear surface of the first semiconductor chip, which is the side opposite to the electrode, and the rear surface of the second semiconductor, which is the side opposite to the electrode, to each other by means of adhesive; and the step of connecting the electrode of the second semiconductor chip to the second wiring electrode of the wiring board by means of a fine metal wire, wherein the adhesive is formed so that the side of the adhesive is inclined from the end portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the sides of the first semiconductor chip at the time of the step of adhering the first semiconductor chip and the second semiconductor chip to each other.

[0018] According to this configuration the adhesive is formed to have an optimized size and form so that the side of the adhesive is inclined from the end portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the sides of the first semiconductor chip at the time of the step of adhering the first semiconductor chip and the second semiconductor chip to each other and, thereby, it becomes possible to prevent the occurrence of defective bonding caused by the impact to the fine metal wires for electrically connecting the second semiconductor chip to the wiring board and to prevent the occurrence of microcracks in the second semiconductor chip. Thereby, a manufacturing method for a semiconductor device of a high reliability molded in resin wherein semiconductor chips are stacked can be provided.

[0019] A manufacturing method for a semiconductor device of the ninth invention is the manufacturing method for a semiconductor device of the eighth invention wherein the fine metal wire is connected to the electrode of the second semiconductor chip after a molten ball is formed of the end of the fine metal wire on the second wiring electrode of the wiring board at the time of the step of connecting the second semiconductor chip to the wiring board by means of the fine metal wire. According to this configuration the fine metal wire is connected to the electrode of the second semiconductor chip after a molten ball is formed of the end of the fine metal wire on the second wiring electrode of the wiring board at the time of the step of connecting the second semiconductor chip to the wiring board by means of the fine metal wire and, therefore, it becomes possible limit the height above the second semiconductor chip of the fine metal wires to a low height.

[0020] A manufacturing method for a semiconductor device of the tenth invention is the manufacturing method for a semiconductor device of the eighth invention wherein the wiring board and a passive part are electrically connected to each other at the time of the step of electrically connecting the wiring board to the first semiconductor chip and wherein the rear surface of the second semiconductor chip and the rear surface of the passive part facing the rear surface of the second semiconductor chip are adhered to each other in the case wherein a spacer is intervened therebetween so that the height of the rear surface of the first semiconductor chip and the height of the spacer become approximately equal at the time of the step of adhering the first semiconductor chip to the second semiconductor chip.

[0021] According to this configuration the wiring board and a passive part are electrically connected to each other at the time of the step of electrically connecting the wiring board to the first semiconductor chip and, therefore, the same working effects as of the eighth invention can be gained in a semiconductor device wherein a plurality of semiconductor chips and a passive part are mounted. In addition, the rear surface of the second semiconductor chip and the rear surface of the passive part facing the rear surface of the second semiconductor chip are adhered to each other in the case wherein a spacer is intervened therebetween so that the height of the rear surface of the first semiconductor chip and the height of the spacer become approximately equal at the time of the step of adhering the first semiconductor chip to the second semiconductor chip and, therefore, the second semiconductor chip can be maintained in a stable condition at the time of connecting the second semiconductor chip to the wiring board by means of fine metal wires even in the case wherein the height of the rear surface of the first semiconductor chip and height of the rear surface of the passive part differ from each other.

[0022] A manufacturing method for a semiconductor device of the eleventh invention is the manufacturing method for a semiconductor device of the eighth invention wherein the wiring board and a passive part are electrically connected to each other and an underfill resin is placed between the wiring board and the first semiconductor chip at the time of the step of electrically connecting the wiring board to the first semiconductor chip and wherein the rear surface of the second semiconductor chip and the rear surface of the passive part facing the rear surface of the second semiconductor chip are adhered to each other in the case wherein a spacer is intervened therebetween so that the height of the rear surface of the first semiconductor chip and the height of the spacer become approximately equal and a material having a thixotropy greater than that of the underfill resin is used for the spacer at the time of the step of adhering the first semiconductor chip to the second semiconductor chip. It is necessary to fill in the underfill resin by injection into a narrow gap (from several .mu.m to several tens of .mu.m) between the first semiconductor chip and the wiring board and, therefore, a low thixotropy is required for the underfill resin while it is necessary for the spacer to be transformed in a plastic manner so that the surface of the spacer and the rear surface of the first semiconductor chip share approximately the same plane in the case wherein an arbitrary load is applied at the time when the second semiconductor chip is mounted and, therefore, it is important for the thixotropic ratio of the spacer to be greater than that of the underfill resin so that the spacer plays a most important role.

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Method for flip chip package and structure thereof
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