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  Semiconductor component having test pads and method and apparatus for testing sameUSPTO Application #: 20070218573Title: Semiconductor component having test pads and method and apparatus for testing same Abstract: A semiconductor component having test pads and a method and apparatus for testing the same is described. In an example, an un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. In another example, a substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads. (end of abstract) Agent: Xilinx, Inc Attn: Legal Department - San Jose, CA, US Inventors: Mohsen Hossein Mardi, Jae Cho, Xin X. Wu, Chih-Chung Wu, Shih-Liang Liang, Sanjiv Stokes, Hassan K. Bazargan USPTO Applicaton #: 20070218573 - Class: 438018000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, With Measuring Or Testing, Electrical Characteristic Sensed, Utilizing Integral Test Element The Patent Description & Claims data below is from USPTO Patent Application 20070218573. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] One or more aspects of the present invention relate generally to testing and manufacture of semiconductor devices and, more particularly, to a semiconductor component having test pads and a method and apparatus for testing the same. BACKGROUND OF THE INVENTION [0002] Semiconductor dice are typically produced by creating several identical devices on a semiconductor substrate, using known techniques of photolithography, deposition, and the like. One type of semiconductor die includes bond pads distributed across the entire surface of the die for supporting bumped contacts. The bond pads are in electrical communication with metal layers disposed on the die and with transistors, resistors, and other electronic circuits integrated within the die. After fabrication, the substrate may be "bumped" by forming bumped contacts on each of the bond pads. The bumped contacts are typically formed of solderable material, such as lead-tin alloy. Bumped dies are often used for flip chip bonding, where the die is mounted face down on a supporting substrate, such as a circuit board or lead-frame, by welding or soldering. The mounted die may then be encapsulated or "packaged" to form an integrated circuit. [0003] In practice, certain physical defects in the substrate, as well as certain defects in the processing of the substrate, inevitably lead to some of the dice being "good" (i.e., fully-functional) and some of the dice being "bad" (i.e., not-fully-functional). Thus, the dice are typically tested before being mounted on the supporting substrate. One type of conventional testing process involves using a testing device to make a plurality of discrete pressure connections to the bond pads on the substrate and provide signals (e.g., power and data signals) to the dice. However, such physical contact may damage the bond pads, which may ruin an entire die or even the entire substrate. [0004] Another type of conventional testing process involves testing the die or substrate subsequent to being bumped by making discrete pressure connections to the bumped contacts. However, such physical contact may damage the bumped contacts, which may also ruin the bumped die/substrate. Specifically, the bumped contacts can become deformed during testing such that they are unusable to attach the die to the supporting substrate. Moreover, testing bumped substrate or die results in additional expense and undue delay in the manufacturing process if the substrate was bad after fabrication. [0005] Accordingly, there exists a need in the art for semiconductor components capable of being more easily tested without causing damage thereto, as well as for improved test procedures for such semiconductor devices. SUMMARY OF THE INVENTION [0006] One aspect of the invention relates to testing a semiconductor component. An un-bumped substrate is obtained having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. Notably, a testing device may contact the test pads without contacting the bond pads, avoiding damage thereto. [0007] Another aspect of the invention relates to fabricating a semiconductor component. A substrate is fabricated having a pattern of bond pads configured to support bumped contacts and a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. The substrate is tested using the plurality of test pads. An insulating layer is formed over the plurality of test pads. The substrate may be bumped to define bumped contacts for the bond pads. The substrate may include at least one semiconductor die formed thereon. The at least one semiconductor die may be mounted to a respective at least one supporting substrate, such as a circuit board or lead-frame. The insulating layer prevents the test pads from interfering with the bumping and mounting processes. [0008] Another aspect of the invention relates to a semiconductor component. A substrate is configured to have at least one conductor layer disposed thereon. The at least one conductor layer includes first portions that define a pattern of bump pads configured to support bumped contacts, and second portions that define a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. A passivation layer is disposed on the at least one conductor layer. The passivation layer includes first openings aligned with the first portions and second openings aligned with the second portions. An insulating layer is disposed within the second openings. [0009] Another aspect of the invention relates to a semiconductor component. A substrate is configured to have at least one conductor layer disposed thereon. The at least one conductor layer includes first portions that define a pattern of bond pads configured to support bumped contacts, and second portions that define a plurality of test pads. Each of the plurality of test pads is in electrical communication with a respective one of the bond pads. A passivation layer is disposed on the at least one conductor layer. The passivation layer includes openings aligned with pairs of the first portions and the second portions. An insulating layer is disposed over the second portions. BRIEF DESCRIPTION OF THE DRAWINGS [0010] Accompanying drawing(s) show exemplary embodiment(s) in accordance with one or more aspects of the invention; however, the accompanying drawing(s) should not be taken to limit the invention to the embodiment(s) shown, but are for explanation and understanding only. [0011] FIG. 1 is a plan view depicting an exemplary embodiment of a substrate configured in accordance with one or more aspects of the invention; [0012] FIG. 2 is a plan view depicting an exemplary embodiment of a semiconductor component configured in accordance with one or more aspects of the invention; [0013] FIG. 3 is a cross-sectional view depicting a portion of the semiconductor component of FIG. 2 taken along the line 3-3; [0014] FIG. 4 is a plan view depicting another exemplary embodiment of a semiconductor component configured in accordance with one or more aspects of the invention; [0015] FIG. 5 is a cross-sectional view depicting a portion of the semiconductor component of FIG. 4 taken along the line 5-5; [0016] FIG. 6 is a flow diagram depicting an exemplary embodiment of a process for fabricating an integrated circuit including a semiconductor component testing process in accordance with one or more aspects of the invention; [0017] FIGS. 7-8 are sequential cross-sectional views of the semiconductor die of FIGS. 2 and 3 corresponding to various stages of the process of FIG. 6; [0018] FIGS. 9-10 are sequential cross-sectional views of the semiconductor die of FIGS. 4 and 5 corresponding to various stages of the process of FIG. 6; and [0019] FIG. 11 is a block diagram depicting an exemplary embodiment of a system for fabricating an integrated circuit including a semiconductor testing unit configured in accordance with one or more aspects of the invention. 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