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  Self-aligned process for nanotube/nanowire fetsUSPTO Application #: 20080026534Title: Self-aligned process for nanotube/nanowire fets Abstract: A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device. (end of abstract) Agent: Scully, Scott, Murphy & Presser, P.C. - Garden City, NY, US Inventors: Phaedon Avouris, Roy A. Carruthers, Jia Chen, Christophe G.M.M. Detavernier, Christian Lavoie, Hon-Sum Philip Wong USPTO Applicaton #: 20080026534 - Class: 438301000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Self-aligned, Source Or Drain Doping The Patent Description & Claims data below is from USPTO Patent Application 20080026534. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a divisional application of U.S. Ser. No. 11/031,168, filed Jan. 7, 2005. FIELD OF THE INVENTION [0002] The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that comprises at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device, i.e., aligned to an edge of the gate region. The present invention also provides a method of fabricating such a CMOS device. BACKGROUND OF THE INVENTION [0003] In the field of molecular nanoelectronics, few materials show as much promise as one-dimensional nanostructures, and in particular carbon nanotubes that comprise hollow cylinders of graphite that have a diameter of a few Angstroms. Nanotubes and other like one-dimensional nanostructures can be implemented in electronic devices, such as, for example, diodes and transistors, depending on the nanoparticles electrical characteristics. One-dimensional nanostructures are unique for their size, shape, and physical properties. For example, carbon-based nanotubes resemble a hexagonal lattice of carbon rolled into a cylinder. [0004] Besides exhibiting intriguing quantum behaviors even at room temperature, carbon-based nanotubes exhibit at least two important characteristics, a nanotube can be either metallic or semiconducting depending on its chirality, i.e., conformational geometry. Metallic nanotubes can carry an extremely large current density with constant resistivity. Semiconducting nanotubes can be electrically switched "on" or "off" as field effect transistors (FETs). The two types may be covalently joined (sharing electrons). These characteristics point to nanotubes as excellent materials for making nanometer-sized semiconductor circuits. Similar properties exist for other one-dimensional nanostructures. [0005] Carbon-based nanotubes and other like one-dimensional nanostructures are thus becoming strategically important for post-Si FET scaling. However, there is no known self-aligned process comparable to conventional CMOS technology. A self-aligned process for a CMOS device including one-dimensional nanostructures would provide a simpler sequence of processing steps as compared to a non-self-aligned process and it reduces processing error that typically occurs when a non-self-aligned process is used. Moreover, a self-aligned process provides a structure having reduced parasitics as compared to a non-self-aligned structure. [0006] In view of the above, there is a need for providing a self-aligned process for fabricating a CMOS device that includes one-dimensional nanostructures, such as nanotubes and nanowires. SUMMARY OF THE INVENTION [0007] The present invention provides a self-aligned one-dimensional nanostructure-containing field effect transistor (FET) as well as a method of fabricating the same. The inventive self-aligned one-dimensional nanostructure-containing FET includes a metal carbide as a contact that is aligned to an edge of the gate region that includes the nanostructures as the device channel. [0008] In the present invention, the term "one-dimensional nanostructure" is used to describe at least one nanotube and/or at least one nanowire. Nanotubes differ from nanowires because nanotubes typically have a hollow cavity, whereas nanowires are completely filled nanomaterials. The term "nanorods" is sometimes used in describing nanowires. One-dimensional nanostructures are structures with nanometer-sized diameters and much, much longer lengths. In other words, the structures have a high aspect ratio and quantum effects become important for these systems. [0009] Specifically and in broad terms, the inventive one-dimensional nanostructure-containing FET comprises: [0010] a substrate comprising at least one gate region located thereon, said at least one gate region comprising a layer of at least one one-dimensional nanostructure; and [0011] a metal carbide contact located on a surface of said substrate that is aligned to an edge of said layer of at least one one-dimensional nanostructure. [0012] In one embodiment of the present invention, the one-dimensional nanostructure is a nanotube. In another embodiment of the present invention, the one-dimensional nanostructure is a nanowire. The at least one one-dimensional nanostructure used in the present invention is typically a carbon-based nanomaterial that is formed utilizing techniques well known to those skilled in the art of nanotechnology. [0013] In addition to providing the aforementioned semiconductor structure, the present invention also provides a method of fabricating the same. The inventive method includes the steps of: [0014] providing a structure that includes at least one gate stack on a surface of a layer of at least one one-dimensional nanostructure; [0015] forming a source/drain metal on the structure including at least said layer of at least one one-dimensional nanostructure; and [0016] forming a metal carbide by reacting said source/drain metal with said layer of at least one one-dimensional nanostructure. [0017] In some embodiments of the present invention, the portion of the layer of the at least one one-dimensional nanostructure, not protected by the at least one gate stack, is doped. In such an embodiment, the metal carbide is formed on the exposed and undoped portion of the layer of at least one one-dimensional nanostructure. [0018] In another embodiment of the present invention, spacers are formed on the sidewalls of the at least one gate stack prior to forming the metal carbide. Spacers are used when a self-aligned silicide anneal process is used. If a non self-aligned silicide anneal is used, the spacers may be omitted. [0019] In another embodiment of the present invention, the at least one one-dimensional nanostructure is embedded within a conductive compound that is generated by the reaction of the source/drain metal with an underlying substrate that includes C or oxide. The embedding occurs during the carbide annealing step mentioned above. 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