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  Self-aligned process for manufacturing a phase change memory cell and phase change memory cell thereby manufacturedUSPTO Application #: 20070057341Title: Self-aligned process for manufacturing a phase change memory cell and phase change memory cell thereby manufactured Abstract: A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element; forming a delimiting structure having an aperture over the resistive element; forming a memory portion of a phase change material in the aperture, the resistive element and the memory portion being in direct electrical contact and defining a contact area of sublithographic extension. The step of forming a memory portion further includes filling the aperture with the phase change material and removing from the delimiting structure an exceeding portion of the phase change material exceeding the aperture. (end of abstract)
Agent: Seed Intellectual Property Law Group PLLC - Seattle, WA, US Inventor: Fabio Pellizzer USPTO Applicaton #: 20070057341 - Class: 257528000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Integrated Circuit Structure With Electrically Isolated Components, Passive Components In Ics The Patent Description & Claims data below is from USPTO Patent Application 20070057341. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a self-aligned process for manufacturing a phase change memory cell and to a phase change memory cell thereby manufactured. [0003] 2. Description of the Related Art [0004] As is known, phase change memory (PCM) elements exploit the characteristics of materials which have the property of changing between two phases having distinct electrical characteristics. For example, these materials may change from an amorphous phase, which is disordered, to a crystalline or polycrystalline phase, which is ordered, and the two phases are associated to considerably different resistivities. [0005] At present, alloys of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can advantageously be used in phase change cells. The chalcogenide that currently offers the best promises is formed by a Ge, Sb and Te alloy (Ge.sub.2Sb.sub.2Te.sub.5) and is widely used for storing information in overwritable disks. [0006] In chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous phase (more resistive) to the polycrystalline phase (more conductive) and vice versa. The characteristics of chalcogenides in the two phases are shown in FIG. 1. As may be noted, at a given read voltage, here designated by Vr, there is a resistance variation of more than 10. [0007] Phase change may be obtained by locally increasing the temperature, as shown in FIG. 2. Below 150.degree. C. both phases are stable. Above 200.degree. C. (temperature of start of nucleation, designated by T.sub.x), fast nucleation of the crystallites takes place, and, if the material is kept at the crystallization temperature for a sufficient length of time (time t.sub.2), it changes its phase and becomes crystalline. To bring the chalcogenide back into the amorphous state, it is necessary to raise the temperature above the melting temperature T.sub.m (approximately 600.degree. C.) and then to cool the chalcogenide off rapidly (time t.sub.1) [0008] From the electrical standpoint, it is possible to reach both critical temperatures, namely the crystallization temperature and the melting point, by causing a current to flow through a resistive element which heats the chalcogenic material by the Joule effect. [0009] The basic structure of a PCM element 1 which operates according to the principles described above is shown in FIG. 3 and comprises a resistive element 2 (heater) and a programmable element 3. The programmable element 3 is made of a chalcogenide and is normally in the polycrystalline state in order to enable a good flow of current. One part of the programmable element 3 is in direct contact with the resistive element 2 and forms the area affected by phase change, hereinafter referred to as the phase change portion 4. [0010] If an electric current having an appropriate value is caused to pass through the resistive element 2, it is possible to heat the phase change portion 4 selectively up to the crystallization temperature or to the melting temperature and to cause phase change. In particular, if a current I flows through a resistive element 2 having resistance R, the heat generated is equal to I.sup.2R. [0011] The use of the PCM element of FIG. 3 for forming memory cells has already been proposed. In order to prevent noise caused by adjacent memory cells, the PCM element is generally associated to a selection element, such as a MOS transistor, a bipolar transistor, or a diode. [0012] All the known approaches are, however, disadvantageous due to the difficulty in finding solutions that meet present requirements as regards capacity for withstanding the operating currents and voltages, as well as functionality and compatibility with present CMOS technologies. [0013] In particular, considerations of a technological and electrical nature impose the creation of a contact area of small dimensions, preferably 20 nm.times.20 nm, between the chalcogenic region and a resistive element. The problem is that these dimensions are much smaller than those that can be obtained with current optical (UV) lithographic techniques, which scarcely reach 100 linear nm. BRIEF SUMMARY OF THE INVENTION [0014] An embodiment of the invention provides a phase change memory cell and a fabrication process thereof, with particular regard to the issue of the poor adhesion between the chalcogenic material and the non-conductive molding layer. [0015] In particular, according to one embodiment of the present invention, a phase change memory cell is fabricated by forming a resistive element and a delimiting structure having an aperture over the resistive element. The memory portion is obtained by filling the aperture with a phase change material, such as a chalcogenic material, followed by removing any phase change material exceeding the aperture. The resistive element and the memory portion are in direct electrical contact and defining a contact area of sublithographic dimension. According to another embodiment of the invention, the memory portion is sealed within the aperture by a sealing structure deposited directly on top of the delimiting structure. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S) [0016] For a better understanding of the present invention, some preferred embodiment thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, in which: [0017] FIG. 1 shows the current versus voltage characteristic of a phase change material; [0018] FIG. 2 shows the temperature versus current plot of a phase change material; [0019] FIG. 3 shows the basic structure of a PCM memory element; [0020] FIG. 4 shows a cross section of a wafer of semiconductor material in a manufacturing step of the cell of FIG. 3, according to the aforementioned patent application; [0021] FIG. 5 shows the layout of some masks used for forming the structure of FIG. 4; Continue reading... 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