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  Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed therebyUSPTO Application #: 20060065909Title: Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby Abstract: Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer. (end of abstract) Agent: Oliff & Berridge, PLC. - Alexandria, VA, US Inventors: William S. Wong, Chinwen Shih, Rene A. Lujan, Eugene Chow USPTO Applicaton #: 20060065909 - Class: 257192000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Heterojunction Device, Field Effect Transistor The Patent Description & Claims data below is from USPTO Patent Application 20060065909. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of Invention [0002] This invention relates to the manufacture of thin films, and more particularly to the manufacture of self-aligned thin film transistors. [0003] 2. Description of Related Art [0004] The patterning of thin film features generally found in microelectronics applications are normally achieved using, for instance, conventional photolithographic and etching processes typically. In the case of thin film transistors, self-aligned transistor structures are generally fabricated using, for example, laser processing, in order to selectively pattern source contact and drain contact and to achieve minimum overlap between the source electrode, the drain electrode and the gate electrode. Moreover, laser processing photolithography is usually complicated because it requires deposition of multilayer thin film mirror stacks to define device features that will subsequently be laser irradiated. SUMMARY OF THE INVENTION [0005] In light of the above-described problems and shortcomings, various exemplary embodiments of the system and methods according to this invention provide for a method of separating a film from a substrate. The method including at least providing a first film on a substrate, providing a second film adjacent to the first film in a longitudinal direction, providing an intrinsically stressed third film over the first and second films, the third film having an interfacial fracture toughness to the first film that is lower than the interfacial fracture toughness of the third film to the second film, and creating a defect at an interface between the third film and the first film in order to initiate a delamination of the third film from the first film because of the strain present in the intrinsically stressed third film. [0006] Moreover, various exemplary embodiments of the systems and methods according to this invention also provide for a method of separating a metal layer and a doped layer such as, for instance, a doped semiconductor layer, from a dielectric layer in a structure that includes the metal layer provided on the doped layer, the metal layer and the doped layer partially covering the dielectric layer. The method includes at least providing a defect at an interface between the doped layer and the dielectric layer and separating the doped layer and overlaying metal layer from the dielectric layer by creating a strain on at least one of the doped layer and the metal layer. [0007] Also, various exemplary embodiments of the methods of this invention also provide for a method of producing a self-aligned thin film transistor, the transistor including a doped layer covering a dielectric layer, and a metal layer covering at least a portion of the doped layer, a strain being created in the metal layer, the method including etching at least a portion of the doped layer that covers a central portion of the dielectric layer and that is not covered by the metal layer so as to create a defect at an interface between the doped layer and the dielectric layer to initiate a delamination of the doped layer and overlaying metal layer from the dielectric layer. [0008] Finally, various exemplary embodiments of the systems of this invention provide for a self-aligned thin film transistor device that includes a first layer, a dielectric layer provided over at least a portion of the first layer, a doped layer provided over a portion of the first layer that is not covered by the dielectric layer, the doped layer being adjacent to at least one substantially vertical surface of the dielectric layer, and a metal layer provided over the doped layer, wherein any portion of the metal layer and the doped layer that covers any non-vertical portion of the dielectric layer surface is removed by a delamination initiated by the creation of a defect at an interface between the doped layer and the dielectric layer surface. BRIEF DESCRIPTION OF THE DRAWINGS [0009] Various exemplary embodiments of the systems and methods of this invention will be described in detail, with reference to the following figures, wherein: [0010] FIG. 1 is a flowchart illustrating a method of selective delamination of thin films according to various exemplary embodiments of this invention; [0011] FIG. 2 is a flowchart illustrating a method of selective delamination of a doped layer and a dielectric layer according to various exemplary embodiments of this invention; [0012] FIGS. 3a-3d schematically illustrate the selective delamination of thin films according to various exemplary embodiments of this invention; [0013] FIGS. 4a-4c schematically illustrate the selective delamination of thin films according to various exemplary embodiments of this invention; [0014] FIGS. 5a-5e schematically illustrate the steps to manufacture a self-aligned semiconductor structure according to various exemplary embodiments of this invention; and [0015] FIGS. 6a-6b schematically illustrate a self-aligned semiconductor device according to various exemplary embodiments of this invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS [0016] These and other features and advantages of this invention are described in, or are apparent from, the following detailed description of various exemplary embodiments of the systems and methods according to this invention. [0017] FIG. 1 is a flowchart illustrating a method of selective delamination of thin films according to various exemplary embodiments of this invention. The method starts with step S100 and continues to step S110, during which a first film is provided. According to various exemplary embodiments, the first film is provided over a substrate. Next, at step S120, a second film is also provided over the same substrate. During step S120, a second film is provided on the substrate and, according to various exemplary embodiments, is adjacent to the first film that was provided on the substrate during step S110. According to various exemplary embodiments, the first film and the second film have dissimilar surface energies. Accordingly, two interfaces are created with two dissimilar adhesion energies, a first interface between the first film and the substrate, and a second interface between the second film and the substrate. According to various exemplary embodiments, one interface has a weak adhesive energy compared to the other. Moreover, the applied stress on the film will cause the region with the interface with a weak adhesion energy to delaminate, while the region with the interface with the stronger adhesion energy does not delaminate. According to various exemplary embodiments, the strain in the film can be created by a variety of factors, such as, for instance, residual film stress, thermal expansion coefficient mismatch, lattice mismatch between the two films, and the like. According to various exemplary embodiments, when the film delaminates, the elastic energy per unit area in the released film, or the energy release rate, must be greater than the interfacial fracture toughness at the interface between the two films in order for one film to release. [0018] After the second film is provided adjacent to the first film and over the substrate, control continues to step S130, during which a buffer layer is provided over the first and second films. Next, control continues to step S140, during which a stressed top film layer is provided over the buffer layer. According to various exemplary embodiments, the stressed top film layer has a tensile stress, resulting in a strain energy that is greater than the adhesive energy of the first interface between the first film and the substrate, but the strain energy of the stressed top film layer is less than the adhesion energy between the second film and the substrate. [0019] After the stressed top film layer is provided over the buffer layer during step S140, control continues to step S150. During step S150, a portion of the buffer layer is etched in order to introduce an edge defect which will initiate an energy release through delamination of the interface between the first film and the buffer layer. According to various exemplary embodiments, the delamination can also be initiated by thermal or radiative annealing of the stressed film. Similarly, altering the geometry and roughness of a portion of the underlying surface may create an adhesion energy contrast at the interface with the overlaying stressed film. According to various exemplary embodiments, because the adhesive energy between the first film and the substrate is larger than the strain energy that results from the tensile stress applied to the top film, the delamination will continue along the weak interface between the first film and the buffer layer until the delamination reaches the interface between the second film and the buffer layer. When the delamination reaches the interface between the second film and the buffer layer, the delamination stops. In effect, the interface between the second layer and the buffer layer is anchoring the portion of the buffer layer that is over the second film. According to various exemplary embodiments, the delamination is anchored by the second film because the strain energy of the stressed top film layer is smaller than the adhesive energy at the interface between the second film and the buffer layer. When the delamination of the first film is complete, then control continues to step S160, where the method ends. [0020] FIG. 2 is a flowchart illustrating a method of selective delamination of a doped layer from a dielectric layer, according to various exemplary embodiments of this invention. The method starts in step S200 and continues to step S210, during which a doped layer and a dielectric layer are provided on an amorphous silicon layer. According to various exemplary embodiments of this invention, the amorphous silicon layer is that of a thin film transistor, and the doped layer is provided over the entire surface of the dielectric layer, and extends on each side of the dielectric layer over the amorphous silicon layer. Next, control continues to step S220, during which a metal layer is provided over the doped layer and thus covers both the doped layer and the dielectric layer. The metal layer may then be patterned in order to define source and drain contacts on the thin-film transistor. According to various exemplary embodiments, the metal layer is provided over outside portions of the dielectric layer and extends on each side of the dielectric layer over the doped layer. Accordingly, although the entire dielectric layer is covered by the doped layer, only outside portions of the doped layer are covered by the metal layer, i.e., a central portion of the doped layer and of the dielectric layer is not covered by the metal layer. Next, control continues to step S230, during which a defect is provided at an interface between the doped layer and the dielectric layer in a portion that is not covered by the metal layer. Continue reading... Full patent description for Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby patent application. Patent Applications in related categories: 20080105900 - Fet channel having a strained lattice structure along multiple surfaces - A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. 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