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Scanning latches using selecting array

Scanning latches using selecting array description/claims

The present application is a continuation of U.S. patent application Ser. No. 10/896,505 (Atty. Docket No. AUS920040243US1), filed on Jul. 22, 2004, and entitled, “Scanning Latches Using Selecting Array,” which is incorporated herein by reference.

The parent application is related to U.S. Pat. No. 7,047,468, application Ser. No. 10/670,832, issued on May 16, 2006, and incorporated herein by reference in its entirety.

The present invention relates in general to the field of computers, and in particular to the observation and manipulation of data in state holding elements. Still more particularly, the present invention relates to a method and system for reading and writing latch data by selecting a specific latch through the use of a line selector.

Computing processor logic is typically made up of multiple clusters of combinatorial logic (hereinafter referred to as “logic”) and data latches. The logic executes machine instructions to manipulate data, and the data latches store data, including input data being input into logic as well as output data being output from the logic after manipulation. A typical collection of logic and latches is shown in FIG. 1a as logic/latch array 100.

Logic/latch array 100 is made up of multiple state holding elements 102 (typically latches) and logics 104. Data bits are input into the top state holding elements 102 where the data bits are latched, and at a subsequent clock cycle are applied to one or more logics 104. The results of the operations of the logics 104 are then outputted to one or more other state holding elements 102, and so on until the final results are outputted at the bottom of the logic/latch array 100. A chip is composed of many such blocks of logic and latches.

A common desire when a chip is manufactured is to test whether there are any defects in the manufacturing process that may cause the chip to function differently from that which would result from defect free manufacturing. A test program of data bits (“test vectors”) inputted into the top of logic/latch array 100 will output known predicted results (“result vectors”) from the bottom of the logic/latch array 100 after a known number of clock cycles if the logic/latch array 100 is working properly. However, for a large block of logic, a prohibitively large number of vectors may be required to determine if the logic/latch block is suitably free from defects. Additionally, the existence of feedback and jumps of data as shown by the arrows in FIG. 1a may increase the number of vectors required to detect all manufacturing defects, or may make it impossible to detect certain detects. One solution to the problem of having a large number of vectors is to independently check smaller portions of the logic block. This can be accomplished by setting the state of the internal latches, clocking the system, and reading the results from the latches. By checking the subfunctions between the latches, much smaller numbers of test vectors can be used to gain higher coverage of the faults.

Thus, to check the accuracy of the operation of logic/latch array 100, interim contents, resulting from operations performed by logics 102, of state holding elements 102 are scanned out and inspected. Checking such intermediate operations and their results utilizes techniques such as Level-Sensitive Scan Design (LSSD) tests, Generalized Scan Design (GSD) tests, or other scan design test techniques that enable testing at all levels of VLSI circuit packaging. The principles of the LSSD technique are described, for example, in U.S. Pat. No. 3,783,254, No. 3,784,907 and No. 3,961,252, all to Eichelberger and incorporated by reference in their entirety.

FIG. 1b illustrates latch pairs 106, analogous to the state holding elements 102 shown in FIG. 1a, that are used for scanning data out of a latch array 101. Latch pairs 106 hold intermediate results of operations performed by logics 104 as described above. (For purposes of clarity, FIG. 1b omits representations of logics 104 shown and described in FIG. 1a.) To facilitate trustworthy scans, each latch pair 106 illustrated in FIG. 1b includes a master latch M106 and a slave latch S106. The slave latches S106 are necessary to ensure that data is not lost through timing mishaps that could occur if data bits were to be passed directly from a first master latch to a second master latch.

During a scan-out process, a data bit in a first master latch is first moved to a first slave latch, which then passes the data bit to a second master latch, which then passes the data bit to a second slave latch, and so on until the data bit safely passes through the entire latch array 101. As depicted in FIG. 1b, the latch array 101 of master latches M106 and slave latches S106 is under the clocking control of a first clock (A_clk) for the master latches M106 and a second clock (B_clk) for the slave latches S106. Thus, when a scan-out operation is performed, the data bits are scanned out in a serial manner as depicted, wherein the data bit in master latch M106-1 moves to slave latch S106-1, which passes the data bit to master latch M106-2, which passes the data bit to slave latch S106-2, and so on until the data bit is finally read out of latch array 101 through/from slave latch S106-x.

Referring now to FIG. 2, there is a block diagram of four master/slave latch pairs being scanned. Assume in FIG. 2 that instead of twenty master/slave latch pairs M106/S106, as depicted in FIG. 1b, there are only four master/slave latch pairs M106-1/S106-1 through M106-4/S106-4 in a First-In First Out (FIFO) 206, as depicted. At initial time “T1”, input queue 208 holds data elements “w, x, y, z,” each master latch M106 holds a significant data bit (such as a result of an intermediate operations performed by some piece of logic), each slave latch S106 is empty or in a “don't care” state, and the output queue 210 is empty (or in a “don't care state). At time “T2”, all the data bits are shifted into the available slave latches. Thus, data bit “A” moves from master latch M106-1 to slave latch S106-1, data bit “B” moves from master latch M106-2 to slave latch S106-2, data bit “C” moves from master latch M106-3 to slave latch S106-3, and data bit “D” moves from master latch M106-4 to slave latch S106-4.

Moving on to time “T3”, the data bits are shifted into the master latches either from slave latches or from the external queue. In addition a data bit will be shifted to the output queue. So, data bit “z” from input queue 208 shifts into master latch M106-1, data bit “A” advances from slave latch S106-1 into master latch M106-2, data bit “B” advances from slave latch S106-2 into master latch M106-3, data bit “C” advances from slave latch S106-3 into master latch M106-4, and data bit “D” advances from slave latch S106-4 into output queue 210. (Note that input queue 208 and output queue 210 may also have master/slave latch pairs (not shown) as depicted for FIFO 206.)

Continuing along the time line in FIG. 2, significant data bits are continued to be scanned out of FIFO 206 until time “T9”, at which time all of the leading data bits (w, x, y, z) originally in input queue 208 are scanned into FIFO 206, and all of the significant data bits (A, B, C, D) are scanned out of FIFO 206 into output queue 210.

One significant limitation of the traditional scan chain described in FIGS. 1a-b and FIG. 2 is that all data in the scan chain must be scanned out in a serial manner. Thus, to view a specific scan chain latch, the entire scan chain must be scanned out, and the contents of a specific scan chain latch must be “picked out” as it enters the output queue 210 shown in FIG. 2.

Another limitation of traditional scan chains is that they require the additional slave latches S106 to ensure accurate serial movement through the serial pathway shown in FIG. 1b. Although additional latches are not needed when a logic/latch block stores internal states in master-slave flip-flips, which themselves are pairs of master and slave latches, slave latches S106 are necessary if mid-cycle latches scheme is used, in which data is latched into a first latch on a clock signal rise, and then latched into a second latch on the same clock signal's fall.

Thus, it would be a useful improvement of the prior art to have a system that allows a specific latch to be directly accessed, allowing the examination of the contents of only that specific latch, without adding additional storage elements to the system.

The present invention is therefore directed to a method and system for directly accessing internal data from a specific latch in a matrix array of latches. The matrix array includes vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of each latch can be selectively accessed.

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• Utility Patent

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