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  Scannable dynamic logic latch circuitUSPTO Application #: 20080100344Title: Scannable dynamic logic latch circuit Abstract: A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the logic circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock. (end of abstract)
Agent: Ibm Corp (wsm) C/o Winstead Sechrest & Minick P.C. - Dallas, TX, US Inventors: Hung C. Ngo, Jente B. Kuang, James D. Warnock, Dieter F. Wendel USPTO Applicaton #: 20080100344 - Class: 326 98 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080100344. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001]The present invention relates to latch circuits and in particular to latch circuits used in conjunction with level sensitive scan design (LSSD) and general scan design (GSD) methodologies. BACKGROUND INFORMATION [0002]Modern data processing systems may perform Boolean operations on a set of signals using dynamic logic circuits. Dynamic logic circuits are clocked. During the precharge phase of the clock, the circuit is preconditioned, typically, by precharging an internal node (dynamic node) of the circuit by coupling to a power supply rail. During an evaluate phase of the clock, the Boolean function being implemented by the logic circuit is evaluated in response to the set of input signal values appearing on the inputs during the evaluate phase. (For the purposes herein, it suffices to assume that the input signals have settled to their "steady-state" values for the current clock cycle, recognizing that the input value may change from clock cycle to clock cycle.) Such dynamic logic may have advantages in both speed and the area consumed on the chip over static logic. However, the switching of the output node with the toggling of the phase of the clock each cycle may consume power even when the logical value of the output is otherwise unchanged. [0003]This may be appreciated by referring to FIG. 1A illustrating an exemplary three-input OR dynamic logic gate and the accompanying timing diagram, FIG. 1B. This type of logic gate is referred to in the literature as a Domino logic gates since state changes ripple through cascaded circuits when the clock signal evaluates the dynamic node like "Dominos" falling. [0004]Dynamic logic 100, FIG. 1A, includes three inputs a, b and c coupled to a corresponding gate of NFETs 102a-102c. During an evaluate phase of clock 104, N.sub.1, NFET 106 is active, and if any of inputs a, b or c are active, dynamic node 108 is pulled low, and the output OUT goes "high" via inverter 110. Thus, referring to FIG. 1B, which is illustrative, at t.sub.1 input a goes high during a precharge phase N.sub.2 of clock 104. During the precharge phase N.sub.2 of clock 104, dynamic node 108 is precharged via PFET 112. Half-latch PFET 114 maintains the charge on dynamic node log through the evaluate phase, unless one or more of inputs a, b or c is asserted. In the illustrative timing diagrams in FIG. 1B, input a is "high" having a time interval t.sub.1 through t.sub.2 that spans approximately 21/2 cycles of clock 104, which includes evaluation phases, 116 and 118. Consequently, dynamic node 108 undergoes two discharge-precharge cycles, 124 and 126. The output node similarly undergoes two discharge-precharge cycles, albeit with opposite phase, 124 and 126. Because the output is discharged during the precharge phase of dynamic node 108, even though the Boolean value of the logical function is "true" (that is, "high" in the embodiment of OR gate 100) the dynamic logic dissipates power even when the input signal states are unchanged. [0005]Additionally, dynamic logic may be implemented in a dual rail embodiment in which all of the logic is duplicated, one gate for each sense of the data. That is, each logic element includes a gate to produce the output signal, and an additional gate to produce its complement. Such implementations may exacerbate the power dissipation in dynamic logic elements, as well as obviate the area advantages of dynamic logic embodiments. [0006]Selection circuits, including shifting circuits and multiplexers, are used extensively within computer systems. Some of these selection circuits require multiple levels of selection, for example, a first input is selected from a plurality of first inputs wherein each of the first inputs are additionally selected from a plurality of second inputs. Computer systems employing dynamic logic may find that it is difficult to implement selection circuits for single and multilevel selection from many inputs because of the limitations of required precharge and evaluation times as well as the fact that outputs are not held during the precharge cycle. [0007]Limited switching dynamic logic (LSDL) circuits produce circuits which mitigate the dynamic switching factor of dynamic logic gates with the addition of static logic devices which serve to isolate the dynamic node from the output node. Additionally, LSDL circuits and systems maintain the area advantage of dynamic logic over static circuits, and further provide both logic senses, that is, the output value and its complement. [0008]Level Sensitive Scan Design (LSSD) methodology is well known to the prior art. Basically the LSSD methodology is a system design in which the device under test has a plurality of storage elements, i.e., latches or registers, that are concatenated in one or more scan chains and are externally accessible via one or more serial inputs and outputs. Storage elements that are not so concatenated are usually memory or other special macros that are isolated and can be tested independently. This LSSD methodology ensures that all logic feedback paths are gated by one or more of these concatenated storage elements, thereby simplifying a sequential design into subsets of combinational logic sections. [0009]These basic design concepts, in conjunction with the associated system and scan clocking sequences, greatly simplify the test generation, testing, and the ability of diagnosing very complex logic structures. In such a design every latch can be used as a pseudo Primary Input (PI) and as a pseudo Primary Output (PO), in addition to the standard Primary Inputs and standard Primary Outputs, to enhance the stimulation and observability of the device being tested or diagnosed. Typically LSSD latches are implemented in a configuration having master (L1) and slave (L2) latches where each master latch (L1) has two data ports and may be updated be either a scan clock or a functional clock and each slave latch (L2) has but one clock input that is out of phase with both L1 scan and functional clocks. Scanning is done using separate A and B scan clocks. [0010]The strategy of diagnosing these LSSD circuits has been established and evolving for many years. The primary characteristic of deterministic or pre-determined LSSD patterns is that each pattern is independent from every other pattern and each pattern consists of Primary Inputs, Clocks, a Load, and an Unload sequence. Such LSSD circuits may have thousands of patterns depending upon the size and structure of the logic. During diagnostics, one or more failing patterns are identified and fault simulation is performed on the failing pattern (Load, Primary Inputs, System Clocks, and Unload sequence). The circuit states can be quickly achieved by reviewing and simulating the falling pattern load, any Primary Inputs, System Clocks, and measures. Passing patterns may also be used to eliminate potential faults that the identified failing patterns marked as potential candidates. [0011]However this method of diagnosing of such complex logic structures to determine the devices that have failed functional testing is very time consuming and difficult and is even more difficult when the circuit designs are sequential in nature and utilize a functional pattern test methodology as found in LSSD circuits. General Scan Designs (GSD) circuits are similar and well known to the art. [0012]The testing and diagnosis of such complex circuits (LSSD and GSD) can be greatly simplified by adopting a design-for-test methodology that reduces the sequential circuit in partitions of combinational logic and allows access to the storage elements within the circuit during the testing process. This structural test methodology in conjunction with such scan based designs allows for effective functional and structural testing approaches. [0013]Both, functional and structural logic test methodologies have unique advantages. Structural logic testing benefits include, ease of test pattern generation, simpler diagnostic methods, lower test pattern data volumes, specific fault targeting, high test coverage and precise test effectiveness measurement. Alternatively, functional testing can be applied at-speed, tests the actual device application functions, and closely emulates the operating environment during test. However, functional testing is sequential in nature and thus must rely on previous events or states of the logic for each subsequent pattern. [0014]Functional fails are generally very difficult to diagnose since detail understanding of the logic circuit design and functional fail behavior is necessary and using the prior art techniques requires that test engineers and designers dedicate many hours and several diagnostic iterations to understand and diagnose the failure mechanism. [0015]This basic problem complicates the diagnostic process by the need to track the structure's logical states for several previous events. This is required so that the failing vector can be analyzed with the proper values of each logic circuit at the time and point of failure. [0016]Therefore, there are compelling economic reasons to electrically diagnose any fault in the circuit to within a couple of logic blocks or a dozen or so transistor devices as rapidly as possible. It is also desirable that the diagnostic process between the electrical model and the physical location be correlated by providing conventional physical failure analysis (PFA) tools with an precise physical location for the potential defect. [0017]Therefore, there is a need for computing circuitry that combines front end dynamic logic circuits with a static latch circuit to achieve low power and high performance while incorporating features that are compatible with scanning architectures such as LSSD and GSD. SUMMARY OF THE INVENTION [0018]Scan latch circuitry is configured to have a front end comprising at least one dynamic logic gate that has a logic tree that performs the normal Boolean logic operation combined with scan circuitry that has a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the scan latch circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive to a logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock. The static output latch holds states of the evaluated dynamic node during the pre-charge phase of the scan clock and the normal clock. The output of the static latch may have individual buffers for driving a normal data path and the scan chain path. [0019]The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [0020]For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings in which; Continue reading... Full patent description for Scannable dynamic logic latch circuit Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Scannable dynamic logic latch circuit patent application. Patent Applications in related categories: 20080238485 - Semiconductor integrated circuit device - A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Scannable dynamic logic latch circuit or other areas of interest. ### Previous Patent Application: Source driver and level shifting apparatus thereof Next Patent Application: Hybrid logic/interconnect circuit in a configurable ic Industry Class: Electronic digital logic circuitry ### FreshPatents.com Support Thank you for viewing the Scannable dynamic logic latch circuit patent info. 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