Sacrificial metal spacer dual damascene invention

Abstract: A method and structure for a dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, creating sacrificial tungsten sidewall spacers in the troughs, patterning the laminated insulator stack, removing the sacrificial sidewall spacers, forming vias in the patterned laminated insulator stack, and depositing a metal liner and conductive material into the vias and troughs, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.

This application is a divisional of U.S. patent application Ser. No. 10/984,439 filed on Nov. 9, 2004, which is a divisional of Ser. No. 10/202,134 filed on Jul. 24, 2002.

The present invention generally relates to integrated circuit design, and more particularly to damascene fabrication using sacrificial metal spacers to aid in the fabrication process.

Dual damascene processing in soft, non-silicon containing intermetal dielectrics, such as SiLK®, available from Dow Chemical Company, NY, USA, or FLARE®, available from Honeywell, NJ, USA. (both materials are polyarylenes (PAE)) is extremely difficult at sub 0.25 micron dimensions because of etch bias, undercut corner erosion, etc., and other problems frequent during RIE processing. Additionally, the traditional argon sputter cleans resputtered PAE into the via bottom and onto the underlying metal (i.e. copper or tungsten) surface, resulting in degraded contact interface properties. Although only argon sputtering is given as an example, all methods of directional sputter cleaning, including reactive ion etching (i.e. hydrogen doped) methods are associated with these problems. PAE-type materials are much softer than oxides, and have much lower thermal conductivity, and are not oxygen or water diffusion barriers. Therefore, in general, they have much worse dielectric properties than oxide.

Conventional methods of performing a dual damascene process is through multiple photoresist mask and etch steps. Here, a single level photoresist profile is formed on a layer deposited dielectric and a via pattern is formed by etching to a first interlevel in the dielectric material. At this point in the process the via is only partially etched. The photoresist is then stripped and a second single layer photoresist profile is formed on the dielectric surface to form an interconnect pattern to a second interlevel in the dielectric material. The interconnect is then formed by etching. Coincident with etching the interconnect, the via is etched such that interconnects in underlying substrate layers are exposed to allow electrical contact. However, aligning the photoresist profiles is a problem using this method. For example, if the two photoresist profiles are not aligned correctly, then intersecting features in the dielectric material will be misaligned. That is, a conductive line associated with the first photoresist pattern may not correctly intersect a via associated with the second photoresist profile. These alignment errors can be corrected by making the intersecting features oversized, but this takes away from the overall goal of reducing the size of connecting lines and vias. Thus, alignment problems reduce yields, and increase cost and the complexity of integrated circuit processes.

The trench and via profiles are greatly affected during dual damascene processing, due to the poor etching selectivity between the photoresist and the low dielectric constant dielectrics (low k dielectrics) while oxygen plasma removes the photoresist layer. Moreover, the low k dielectrics fill the gaps between the wiring lines in order to prevent parasitic capacitance, which occurs when the distance between subsequent wiring lines is reduced. Thus, in order to avoid the problems associated with conventional dual damascene manufacturing techniques, complicated processes and structures are implemented.

Even proposed solutions to these rather complex processes, such as the process described in U.S. Pat. No. 6,017,817, issued to Chung, et. al., “Method of Fabricating Dual Damascene,” the complete disclosure of which is herein incorporated by reference, does not provide an adequate solution to the problem of eliminating the PAE sputtering into the via bottom. Rather, these processes merely aim to reduce the effective capacitance of the low k dielectrics. In fact, these conventional techniques offer little, if any, solutions to such problems as etch bias and undercut corner erosion in the integrated circuit. Furthermore, the conventional processes do nothing to improve degraded contact interface properties due to the PAE sputtering into the via bottom.

Therefore, there is a need for a new and improved technique of damascene processing which overcomes the limitations of the conventional designs, and which improves the damascene process window, and/or eliminates the PAE sputtering into the via bottom by using a deep etch process.

In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional dual damascene fabrication techniques the present invention has been devised, and it is an object of the present invention to provide a structure and method for a sacrificial metal spacer damascene (single and dual) fabrication technique. Another object of the present invention is to provide a new and improved technique of dual damascene processing which overcomes the limitations of the conventional designs. Still, another object of the present invention is to improve the dual damascene process window. Yet another object of the present invention is to eliminate the problem of PAE sputtering into the via bottom by using a deep etch process. It is still another object of the present invention to use metal spacers to aid in fabricating damascene wires/vias.

In order to attain the objects suggested above, there is provided, according to one aspect of the invention a dual damascene interconnect structure comprising a substrate, an insulator layer above the substrate, a hardmask over the insulator layer, patterned troughs defined into the hardmask, and patterned vias defined into the insulator layer, wherein the hardmask includes sacrificial sidewall spacers to aid in forming the dual damascene interconnect structure.

According to the present invention, the method of forming a dual damascene interconnect structure in a semiconductor substrate comprises first forming wiring lines in a metallization layer over a substrate. The next step is shaping a laminated insulator stack above the metallization layer. Then, a hardmask is patterned over the laminated insulator stack. After this, troughs are formed in the hardmask. Next, sacrificial sidewall spacers are created in the troughs. Upon completion of this step, the laminated insulator stack is patterned. Then, the sacrificial sidewall spacers are removed. Next, vias are formed in the patterned laminated insulator stack. The next step is depositing a metal liner into the vias and troughs, and finally, conductive material is deposited over the liner, wherein the laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene. The laminated insulator stack comprises oxide and a dielectric layer further comprising polyarylene. The sacrificial sidewall spacers preferably comprise tungsten. The step of depositing prevents the laminated insulator stack from sputtering into the vias. Moreover, the step of depositing comprises cleaning the vias and troughs, optionally performing a reactive ion etching or argon sputter cleaning, depositing a plurality of metal layers over the vias and troughs, and depositing copper in the vias and troughs.

Alternatively, the method comprises first forming a trough mask pattern into a hardmask layer over a substrate. Then, a via mask pattern is patterned into an insulator layer, wherein the insulator layer is below the hardmask layer. Next, sidewall spacers are selectively etched in the hardmask layer. After this, troughs are created, which are defined by the trough mask pattern. Then, the sidewall spacers are removed, and finally, vias are created, which are defined by the via mask pattern. Still alternatively, the process of first etching the troughs and then etching the vias can be reversed, wherein the vias are etched prior to the troughs.

There are several benefits of the present invention. For example, the present invention provides a novel structure and method for forming a sacrificial metal spacer dual damascene structure as well as a single damascene structure. Also, the present invention provides a new and improved technique of dual damascene and single damascene processing which overcomes the limitations of the conventional designs. Additionally, the present invention improves the dual damascene process window. Furthermore, the present invention eliminates the problem of PAE sputtering into the via bottom by using a deep etch process. Finally, the present invention uses metal (tungsten) spacers to aid in fabricating damascene wires/vias.