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Ruthenium silicide wet etchRelated Patent Categories: Etching A Substrate: Processes, Nongaseous Phase Etching Of SubstrateRuthenium silicide wet etch description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20050263489, Ruthenium silicide wet etch. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a continuation of prior application Ser. No. 10/421,976 filed Apr. 23, 2003, now U.S. Pat. No. 6,908,569, which is a divisional application of prior application Ser. No. 10/165,801 filed Jun. 7, 2002, which is a divisional application of prior application Ser. No. 09/799,791 filed Mar. 5, 2001, now U.S. Pat. No. 6,498,110, all of which are hereby incorporated by reference in their entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention relates to silicon integrated circuit processing and, more particularly, to a process for selectively removing ruthenium silicide from a semiconductor substrate. [0004] 2. Description of the Related Art [0005] Semiconductor devices are typically made up of varying levels of components, each of which are formed from different materials. During the process of fabricating a semiconductor device, the device layers are repeatedly subjected to high temperature processes that can result in diffusion of species between layers. Diffusion of species of atoms or molecules, such as oxygen, for example, can result in degraded performance of different components of the semiconductor device. This problem occurs in a number of different semiconductor devices such as interconnects or capacitors. [0006] A capacitor structure within an integrated circuit typically comprises an insulating dielectric layer sandwiched between a lower and upper conducting electrode. This provides the capacitor structure with a desired capacitance C, that varies proportionally with the dielectric constant, k, of the dielectric layer and the area, A, of the electrodes. However, due to the limitations of known manufacturing methods, the typical dielectric layer often suffers from a substantially large concentration of oxygen vacancy defects. In particular, an oxygen vacancy exists whenever the crystal structure of an oxide dielectric is missing an oxygen atom. Unfortunately, the presence of oxygen vacancies within the dielectric causes the dielectric layer to have a decreased dielectric constant as well as a decreased electrical resistance. Thus, a capacitor structure formed of such a dielectric layer usually provides a decreased capacitance, thereby reducing the charge deposited on the electrodes of the capacitor structure in response to a specific voltage differential applied across the electrodes. [0007] Furthermore, the problems associated with oxygen vacancies within dielectric materials are becoming more apparent as integrated circuits are formed with increasingly smaller circuit elements. For example, high density Dynamic Random Access Memory (DRAM) devices requiring a large number of capacitor structures demand the electrodes of each capacitor structure to have a relatively small area. Thus, in order to provide a sufficient capacitance in response to the reduced area, A, of the electrodes, dielectric materials having a relatively large dielectric constant, k, otherwise known as high-k dielectric materials, are required. However, known high-k dielectric materials, such as tantalum pentoxide (Ta.sub.2O.sub.5), barium strontium titanate (BST), barium titanate (BT) lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT), require the presence of oxygen atoms throughout their crystal structures. Furthermore, the dielectric constant and the electrical resistance of these high-k materials are especially sensitive to the presence of oxygen vacancies. Thus, these capacitor structures are more likely to be formed with an insufficient capacitance for developing a detectable charge as well as an insufficient resistance for maintaining the detectable charge. [0008] To address the problem of oxygen vacancies in dielectric materials, manufacturers often subject DRAM integrated circuits to re-oxidation anneals. For example, DRAM integrated circuits are usually exposed to an annealing process which heats the integrated circuit in an oxidizing environment subsequent to the deposition of the dielectric material and prior to the deposition of the upper electrode so as to source oxygen atoms to the exposed dielectric material to thereby reduce the concentration of oxygen deficiencies. Disadvantageously, however, during the annealing operation the oxygen is known to diffuse through the dielectric layer and seep into the underlying bottom electrode, thus adversely affecting the electrical properties of the electrode. In particular, the bottom electrode is typically formed on a silicon based substrate surface and the silicon is known to migrate upwardly from the substrate surface into the bottom electrode. During the annealing operation, silicon that has diffused upwardly into the bottom electrode can react with the oxygen to form silicon dioxide (SiO.sub.2). The formation of silicon dioxide in the bottom electrode is undesirable as it has shown to result in open contacts. This problem is especially prevalent in capacitors having bottom electrodes made of platinum, ruthenium oxide, or other metals that are particularly susceptible to silicon permeation. [0009] To address this problem, a barrier layer can be interposed between the bottom electrode and the underlying silicon substrate surface to inhibit silicon from diffusing upwardly into the bottom electrode. In fact, one such method is disclosed in U.S. patent application Ser. No. 09/141,240 assigned to Micron Technology which teaches using a ruthenium silicide (RuSi.sub.x) liner as a silicon diffusion barrier in Metal-Insulator-Metal (MIM) capacitor modules. As described in the above mentioned pending U.S. patent application, ruthenium silicide (RuSi.sub.x) is preferably deposited onto the silicon substrate surface using a chemical vapor deposition (CVD) method that is well known in the art. However, the CVD process is known to deposit RuSix on the edges and backside of the wafer as well as any other unmasked surfaces such as clamping tools or other equipment used during deposition. As a consequence, the excessive RuSi.sub.x deposits have to be removed from the substrate surface prior to completion of wafer processing. [0010] Although a number of etchants have been developed for removing ruthenium metal, there is presently no known chemistry that can effectively remove ruthenium silicide in bulk. Since the use of ruthenium silicide as a barrier liner is a relatively novel idea that shows potential for a wide range of applications in semiconductor fabrication, it can be appreciated that an appropriate etchant for removing ruthenium silicide is highly desired. Hence from the foregoing, it will be appreciated that there is a need for an etchant that can effectively remove ruthenium silicide. To this end, this is a particular need for an etching process that is simple, cost effective, and can selectively remove ruthenium silicide in bulk from a substrate surface. SUMMARY OF THE INVENTION [0011] The aforementioned needs are satisfied by the present invention which teaches a method of selectively removing ruthenium silicide (RuSi.sub.x) from a surface. In one aspect, the present invention comprises a method of using chlorine and fluorine containing chemicals to remove RuSi.sub.x from a surface. In particular, the method comprises exposing the surface containing ruthenium silicide to a solution containing chlorine and fluorine containing chemicals such that the solution reacts with the ruthenium silicide film to form water-soluble reaction products. Furthermore, subsequent to reacting ruthenium silicide with said solution, the method comprises rinsing the surface to further dissolve and remove reactants and products formed as a result of the interaction between RuSi.sub.x and the etching solution. [0012] In one embodiment, the surface containing ruthenium silicide is exposed to an aqueous solution containing chlorine- and fluorine-containing chemicals. Furthermore, the same aqueous solution is used to dissolve and remove the reaction products so that the formation and dissolution of soluble products can be performed in the same reaction tank using substantially the same solution. However, in other embodiments, chlorine- and fluorine-containing chemicals may be obtained from a gaseous source and a separate aqueous solution may be used to dissolve and flush the reaction products remaining on the surface. For instance, chlorine gas can be mixed with HF solution and water to form the etchant solution. Alternatively, the etchant solution can be prepared by bubbling Cl.sub.2 and HF gas into water. [0013] In another aspect, the present invention comprises a hypochlorite salt based solution that can selectively etch RuSi.sub.x from a substrate surface. In one embodiment, the solution may comprise approximately 0.6% potassium hypochlorite (KOCl), 0.7% hydrofluoric acid (HF), and 98.7% D.I. water by weight. In another embodiment, the solution comprises KOCl, HF, and water combined in the volume ratio of 3:1:50 respectively. Furthermore, the KOCl and HF used in this embodiment are off-the-shelf aqueous solutions premixed at concentration levels of 11% and 49% respectively. Advantageously, the ingredients of the solution are relatively inexpensive and commonly available. Furthermore, the solution can be made using conventional laboratory techniques that are simple and convenient to implement. [0014] In yet another aspect, a method of removing ruthenium silicide (RuSi.sub.x) from a substrate surface is provided wherein the method comprises exposing the RuSi.sub.x to a hypochlorite salt based solution. In one embodiment, the RuSi.sub.x is immersed in the hypochlorite salt based solution for approximately 1-10 minutes. Furthermore, the hypochlorite salt based solution comprises potassium hypochlorite, hydrofluoric acid, and D.I. water combined in the volume ratio of 3:1:50 respectively using 11% KOCl and 49% HF aqueous solutions. The solution effectively dissolves the RuSix on the substrate surface and the substrate surface may comprise the back side, edges, or recessed areas on a wafer. Advantageously, the etching process does not require specialized equipment or techniques as the substrates can be batch processed in open tanks that are commonly used in wet chemistry processing. Of course, the same process chemistry can be applied through many wet process tools available to those skilled in the art. These tools include but are not limited to, spray process, spin etch, and brush scrub process technologies. [0015] In yet another aspect, the present invention provides a method of selectively removing ruthenium silicide (RuSi.sub.x) from a substrate surface without substantially affecting other non-RuSi.sub.x areas that are not masked with photoresist or other coating. In particular, the method uses a hypochlorite salt based solution that is capable of selectively etching RuSi.sub.x from a surface without adversely affecting other exposed material, such as oxide layers or the like. Furthermore, one or both sides of the substrate surface may be selectively processed. In one embodiment, the edge of the wafer is selectively processed in a spin-etch tool. Advantageously, the solution is formulated to remove RuSi.sub.x at a much faster rate than it removes other material on the substrate surface, which in most instances effectively obviates the need of masking the substrate surface to protect other material on the substrate from the etchant. [0016] Advantageously, the present invention provides an etchant that can effectively remove ruthenium silicide (RuSi.sub.x) from a substrate surface while there is presently no other chemicals known in the art that is able to even marginally etch RuSi.sub.x. In fact, the use of RuSi.sub.x itself is relatively novel in semiconductor fabrication and its numerous advantages are disclosed in the above mentioned copending application. However, it can be appreciated that these advantages cannot be fully realized without an effective method of removing excess RuSi.sub.x from the substrate surface. Thus, the present invention fulfills an important need by providing a relatively simple and cost-effective method of removing ruthenium silicide from a substrate surface so that RuSi.sub.x can be widely used in integrated circuit fabrication. Furthermore, the method can be adapted to selectively remove RuSi.sub.x from a substrate surface without masking the substrate which further reduces the number of processing steps and the risk of incurring defects. [0017] From the foregoing, it will be appreciated that the aspects of the present invention provide a method of selectively removing ruthenium silicide (RuSi.sub.x) from a substrate surface. In particular, the invention provides a novel method of etching RuSi.sub.x by exposing the RuSi.sub.x to a hypochlorite salt based solution wherein the solution effectively dissolves the RuSi.sub.x without noticeably affecting other material on the substrate surface. These and other advantages of the present invention will become more apparent from the following description taken in conjunction with the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 is a flow diagram illustrating a process flow for removing ruthenium silicide from a substrate surface in accordance with a preferred embodiment of the present invention; [0019] FIG. 2 is a partial elevational cross-sectional view of a partially fabricated integrated circuit or substrate assembly, showing a conventional capacitor structure formed on a substrate surface prior to the etching process of FIG. 1; [0020] FIG. 3 shows the capacitor structure of FIG. 2 subsequent to the etching process of FIG. 1; Continue reading about Ruthenium silicide wet etch... Full patent description for Ruthenium silicide wet etch Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Ruthenium silicide wet etch patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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