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08/16/07 - USPTO Class 257 |  27 views | #20070187800 | Prev - Next | About this Page  257 rss/xml feed  monitor keywords

Resistor tuning

USPTO Application #: 20070187800
Title: Resistor tuning
Abstract: A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned). (end of abstract)



Agent: Schmeiser, Olsen & Watts - Latham, NY, US
Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Robert M. Rassel, Anthony K. Stamper
USPTO Applicaton #: 20070187800 - Class: 257536000 (USPTO)

Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Integrated Circuit Structure With Electrically Isolated Components, Passive Components In Ics, Including Resistive Element

Resistor tuning description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20070187800, Resistor tuning.

Brief Patent Description - Full Patent Description - Patent Application Claims
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[0001] This application is a divisional of Ser. No. 10/709,115, filed Apr. 14, 2004.

BACKGROUND OF THE INVENTION

[0002] 1. Technical Field

[0003] The present invention relates to methods for tuning (i.e., trimming) resistors of a chip, and more particularly, to a method for tuning resistors of a chip that can be used both before and after chip packaging.

[0004] 2. Related Art

[0005] Conventional manufacturing controls on processes for forming passive devices, such as resistors in CMOS (Complementary Metal Oxide Silicon) chips, fall short of current circuit design requirements. Current industry standard I/O (Input/Output) specifications are exceeding what can be achieved in current manufacturing processes. Within analog and RF (radio frequency) semiconductors, the need for tuning the electrical resistance values of the resistors on an integrated circuit to a specific nominal value is growing to meet complex design specification requirements. Manufacturing excess chips and then sorting for required parameters is one solution, but this is a costly and not consistent with manufacturing techniques. Laser ablation is used to trim in the manufacture of some precision passive devices, but this process is inconsistent with the CMOS/BiCMOS or Analog process flow as a measurement and feedback loop is required as well as individual laser trimming of a multitude of devices on a single chip. A third known solution is to design active controls into the circuitry to compensate for manufacturing variability, but this takes up space, increases complexity, and can lead to trade-offs in performance.

[0006] Therefore, there is a need for a novel resistance structure that can be tuned to a specification. Also, there is a need for a method for tuning the novel resistance structure.

SUMMARY OF THE INVENTION

[0007] The present invention provides a resistor structure, comprising (a) an electrically conducting region; (b) a liner region coupled to the electrically conducting region; and (c) first and second contact regions electrically coupled to the electrically conducting region and the liner region, wherein in response to a current flowing in the electrically conducting region and from the first contact region to the second contact region, a void region in the electrically conducting region expands due to electromigration so as to increase the resistance of the resistor structure between the first and second contact regions.

[0008] The present invention also provides a method for tuning a resistor structure, the method comprising the steps of (a) providing (i) an electrically conducting region, (ii) a liner region coupled to the electrically conducting region, and (iii) first and second contact regions electrically coupled to the electrically conducting region and a liner region; and (b) flowing a current in the electrically conducting region and from the first contact region to the second contact region such that a void region in the electrically conducting region expands due to electromigration so as to increase the resistance of the resistor structure between the first and second contact regions.

[0009] The present invention also provides a providing in the resistor structure (i) a semiconductor region, (ii) an electrically conducting layer formed on the semiconductor region, (iii) a plurality of contact regions electrically coupled to the electrically conducting layer; (b) selecting first and second contact regions of the plurality of contact regions such that if intervals of the electrically conducting layer between the first and second contact regions are replaced by a void region due to electromigration, the resistance of the resistor structure between third and fourth contact regions of the plurality of contact regions is within a pre-determined tolerance of a pre-specified target resistance value; and (c) applying a voltage difference between the first and second contact regions until the intervals of the electrically conducting layer between the first and second contact regions are replaced by the void region due to electromigration

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1A illustrates a cross-sectional view of a resistor structure, in accordance with embodiments of the present invention.

[0011] FIG. 1B illustrates a view along a line 1B-1B of the resistor structure of FIG. 1A.

[0012] FIG. 1C illustrates the resistor structure of FIG. 1A after tuning, in accordance with embodiments of the present invention.

[0013] FIG. 1D illustrates the relationship between the resistance and tuning time of the resistor structure of FIG. 1A, in accordance with embodiments of the present invention.

[0014] FIG. 2A illustrates a top view of another resistor structure, in accordance with embodiments of the present invention.

[0015] FIGS. 2Bi and 2Bii illustrate two views along lines 2Bi-2Bi and 2Bii-2Bii, respectively, of the resistor structure of FIG. 2A.

[0016] FIG. 2C illustrates the resistor structure of FIG. 2A after tuning, in accordance with embodiments of the present invention.

[0017] FIG. 3A illustrates a cross-sectional view of yet another resistor structure, in accordance with embodiments of the present invention.

[0018] FIG. 3B illustrates a view along a line 3B-3B of the resistor structure of FIG. 3A.

[0019] FIG. 3C illustrates the resistor structure of FIG. 3A after tuning, in accordance with embodiments of the present invention.

[0020] FIG. 4A illustrates a top view of yet another resistor structure, in accordance with embodiments of the present invention.

[0021] FIG. 4B illustrates a view along a line 4B-4B of the resistor structure of FIG. 4A.

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Semiconductor device and method of manufacturing the same
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