| Repair of memory hard failures during normal operation, using ecc and a hard fail identifier circuit -> Monitor Keywords |
|
|
 
Repair of memory hard failures during normal operation, using ecc and a hard fail identifier circuitRelated Patent Categories: Error Detection/correction And Fault Detection/recovery, Data Processing System Error Or Fault Handling, Reliability And Availability, Error Detection Or NotificationRepair of memory hard failures during normal operation, using ecc and a hard fail identifier circuit description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070162786, Repair of memory hard failures during normal operation, using ecc and a hard fail identifier circuit. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Technical Field [0002] The present invention relates to memory hard failure repair, and more specifically, to hard failure repair during normal operation using an ECC (Error Correction Code) circuit and a hard fail identifier circuit. [0003] 2. Related Art [0004] Prior art exists which covers detection and repair of hard failures in a memory device during the manufacturing process (i.e., at time zero). Prior art also exists which covers detection and correction of soft errors in a memory device during normal operation (e.g., Error Correction Code). Prior art also exists which covers memory error detection and address disable or device replacement during normal operation. There is a need for a subsystem (and a method for operating the same) in which hard failures are detected and repaired during normal operation of a memory device. SUMMARY OF THE INVENTION [0005] The present invention provides a memory sub-system, comprising (a) a main memory; (b) an ECC (Error Correction Code) circuit electrically coupled to the main memory; and (c) a hard fail identifier circuit electrically coupled to the ECC circuit, wherein the ECC circuit is capable of detecting a first bit fail at a first bit location at a first location address of the main memory, wherein the ECC circuit is further capable of sending an error flag signal to notify the hard fail identifier circuit about the first bit fail, wherein the ECC circuit is further capable of sending the first location address of the first bit fail to the hard fail identifier circuit, wherein the ECC circuit is further capable of sending the first bit location of the first bit fail to the hard fail identifier circuit, wherein the ECC circuit is further capable of repairing data from the first location address and sending the repaired data to the hard fail identifier circuit, wherein the hard fail identifier circuit is capable of, in response to the error flag signal being sent, determining and tracking the number of times of failure occurring at the first location address and the first bit location, wherein the hard fail identifier circuit is further capable of determining whether the number of times of failure at the first location address and the first bit location is equal to a predetermined threshold value, and wherein the hard fail identifier circuit is further capable of, in response to the hard fail identifier circuit determining that the number of times of failure is equal to the predetermined threshold value, sending a threshold reached signal to indicate that the first bit fail is a hard fail. [0006] The present invention provides a memory sub-system operation method, comprising providing a memory sub-system which includes (a) a main memory, (b) an ECC (Error Correction Code) circuit electrically coupled to the main memory, and (c) a hard fail identifier circuit electrically coupled to the ECC circuit; in response to a first bit fail at a first bit location and at a first location address of the main memory occurring, using the ECC circuit to send an error flag signal to the hard fail identifier circuit; in response to the first bit fail occurring, using the ECC circuit to further send the first location address of the first bit fail to the hard fail identifier circuit; in response to the first bit fail occurring, using the ECC circuit to further send the first bit location of the first bit fail to the hard fail identifier circuit; in response to the first bit fail occurring, using the ECC circuit to further repair data from the first location address and send the repaired data to the hard fail identifier circuit; in response to the error flag signal being sent, using the hard fail identifier circuit to determine and track the number of times of failure at the first location address and the first bit location; using the hard fail identifier circuit to further determine whether the number of times of failure is equal to a predetermined threshold value; and using the hard fail identifier circuit to further send a threshold reached signal in response to the hard fail identifier circuit determining that the number of times of failure is equal to the predetermined threshold value. [0007] The present invention provides a memory sub-system, comprising (a) a main memory; (b) an ECC (Error Correction Code) circuit electrically coupled to the main memory; (c) a hard fail identifier circuit electrically coupled to the ECC circuit; (d) a repair circuit electrically coupled to the hard fail identifier circuit; (e) a redundant memory electrically coupled to the main memory and the repair circuit; and (f) a threshold setting circuit electrically coupled to the hard fail identifier circuit, wherein the ECC circuit is capable of detecting a first bit fail at a first bit location at a first location address of the main memory, wherein the ECC circuit is further capable of sending an error flag signal to notify the hard fail identifier circuit about the first bit fail, wherein the ECC circuit is further capable of sending the first location address of the first bit fail to the hard fail identifier circuit, wherein the ECC circuit is further capable of sending the first bit location of the first bit fail to the hard fail identifier circuit, wherein the ECC circuit is further capable of repairing data from the first location address and sending the repaired data to the hard fail identifier circuit, wherein the hard fail identifier circuit is capable of, in response to the error flag signal being sent, determining and tracking the number of times of failure occurring at the first location address and the first bit location, wherein the hard fail identifier circuit is further capable of determining whether the number of times of failure at the first location address and the first bit location is equal to a predetermined threshold value, wherein the hard fail identifier circuit is further capable of, in response to the hard fail identifier circuit determining that the number of times of failure is equal to the predetermined threshold value, sending a threshold reached signal to indicate that the first bit fail is a hard fail, wherein the repair circuit is capable of, in response to the threshold reached signal being sent, determining whether there is an available redundant memory location in the redundant memory, wherein the repair circuit is further capable of, in response to the repair circuit determining that there is an available redundant memory location in the redundant memory, selecting the available redundant memory location of the redundant memory to replace a defective main memory location of the main memory at the first location address, such that whenever the first location address of the first bit fail appears on an address bus of the main memory, the selected redundant memory location is accessed instead of the defective main memory location of the main memory, and wherein the threshold setting circuit is capable of providing the predetermined threshold value to the hard fail identifier circuit. [0008] The present invention provides a novel memory sub-system (and a method for operating the same) in which hard failures in a memory device are detected and repaired during the normal operation of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG. 1 illustrates a block diagram of a memory sub-system, in accordance with embodiments of the present invention. [0010] FIG. 2 shows one embodiment of the hard fail identifier circuit of the memory sub-system of FIG. 1, in accordance with embodiments of the present invention. [0011] FIG. 3 shows a flowchart that illustrates a method for operating the memory sub-system of FIG. 1, in accordance with embodiments of the present invention. [0012] FIG. 4 illustrates another memory sub-system as one embodiment of the memory sub-system of FIG. 1, in accordance with embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION [0013] FIG. 1 illustrates a block diagram of a memory sub-system 100, in accordance with embodiments of the present invention. Illustratively, the memory sub-system 100 comprises a main memory 110, an ECC (Error Correction Code) circuit 112, a redundant memory 114, a hard fail identifier circuit 120, a repair circuit 130, and a threshold setting circuit 140. In one embodiment, the hard fail identifier circuit 120 receives an error flag signal 112a, a word address signal 112b, a bit location signal 112c, and a repaired data signal 112d from the ECC circuit 112. In one embodiment, the hard fail identifier circuit 120 also receives a threshold count signal 140a from the threshold setting circuit 140. Illustratively, the repair circuit 130 receives a threshold reached signal 120b, a word address signal 120c, and a repaired data signal 120a from the hard fail identifier circuit 120. In one embodiment, the repair circuit 130 sends a repaired data signal 130a and a write repaired data signal 130b to the redundant memory 114. In one embodiment, the repair circuit 130 sends a no repair location available signal 130c to indicate that there are no more redundant memory locations in the redundant memory 114 that can be used to replace a defective main memory location in the main memory 110. [0014] FIG. 2 shows one embodiment of the hard fail identifier circuit 120 of FIG. 1, in accordance with embodiments of the present invention. Illustratively, the hard fail identifier circuit 120 comprises a compare circuit 124, a control circuit 122, an entry allocation circuit 128, and a failure stack 126. [0015] In one embodiment, the compare circuit 124 receives the error flag signal 112a, the word address signal 112b, and the bit location signal 112c from the ECC circuit 112 of FIG. 1. In one embodiment, the compare circuit 124 also receives an all address entry signal 126d and an all bit location entry signal 126e from the failure stack 126. Illustratively, the compare circuit 124 also sends a hit signal 124b and an entry location signal 124a to the control circuit 122. In one embodiment, the compare circuit 124 also sends a miss signal 124c to the entry allocation circuit 128. [0016] In one embodiment, the control circuit 122 receives the hit signal 124b and the entry location signal 124a from the compare circuit 124. In one embodiment, the control circuit 122 also receives the repaired data signal 112d and the threshold count signal 140a from the ECC circuit 112 and the threshold setting circuit 140, respectively, of FIG. 1. In one embodiment, the control circuit 122 receives a fail count signal 126b from the failure stack 126. Illustratively, the control circuit 122 also receives a word address signal 126a from the failure stack 126 and forwards the word address signal 126a to the repair circuit 130 of FIG. 1 as the word address signal 120c. In one embodiment, the control circuit 122 sends an increment fail count signal 122a, a remove entry signal 122b, an update age signal 122c, and an entry location signal 122d to the failure stack 126. For illustration, the control circuit 122 also sends the threshold reached signal 120b and the repaired data signal 120a to the repair circuit 130 of FIG. [0017] In one embodiment, the entry allocation circuit 128 receives the miss signal 124cfrom the compare circuit 124. In one embodiment, the entry allocation circuit 128 also receives an all use bit entry signal 126c, an all fail count entry signal 126f, and an all age entry signal 126g from the failure stack 126. Illustratively, the entry allocation circuit 128 also sends an entry location signal 128a to the failure stack 126. It should be noted that the word address signal 112b, the bit location signal 112c (from the ECC circuit 112 of FIG. 1) and the entry location signal 128a (from the entry allocation circuit 128) can be collectively refer to as a set update signal 128b. [0018] In one embodiment, the failure stack 126 comprises multiple entries (like entries 226a, 226b, and 226c). Although the failure stack 126 has many entries, only the three entries 226a, 226b, and 226c of the failure stack 126 are shown in FIG. 2. In one embodiment, the entry 226a comprises a use bit 226a1, an address field 226a2, a bit location field 226a3, a fail count field 226a4, and an age field 226a5. Illustratively, the use bit 226a1 indicates whether the entry 226a is available or unavailable; the address field 226a2 stores address of the fail wordline; and the bit location field 226a3 indicates the location of a bit fail in the fail wordline. In one embodiment, the fail count field 226a4 indicates the number of failure occurrences at an address and at a bit location of the wordline. In one embodiment, the age field 226a5 indicates the time period during which the bit fail entry has been stored or the fail count 226a4 incremented in the entry 226a of the failure stack 126. [0019] Similarly, in one embodiment, the entry 226b comprises a use bit 226b1, an address field 226b2, a bit location field 226b3, a fail count field 226b4, and an age field 226b5. Illustratively, the use bit 226b1, the address field 226b2, the bit location field 226b3, the fail count field 226b4, and the age field 226b5 has the same function as the use bit 226a1, the address field 226a2, the bit location field 226a3, the fail count field 226a4, and the age field 226a5, respectively. [0020] In one embodiment, similarly, the other entries of the failure stack 126 comprise components similar to those of the entry 226a. Continue reading about Repair of memory hard failures during normal operation, using ecc and a hard fail identifier circuit... Full patent description for Repair of memory hard failures during normal operation, using ecc and a hard fail identifier circuit Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Repair of memory hard failures during normal operation, using ecc and a hard fail identifier circuit patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Repair of memory hard failures during normal operation, using ecc and a hard fail identifier circuit or other areas of interest. ### Previous Patent Application: Information recording medium, recording apparatus and method for an information recording medium, reproducing apparatus and method for an information recording medium computer program for controlling record or reproduction, and data structure including co Next Patent Application: Monitoring vrm-induced memory errors Industry Class: Error detection/correction and fault detection/recovery ### FreshPatents.com Support Thank you for viewing the Repair of memory hard failures during normal operation, using ecc and a hard fail identifier circuit patent info. IP-related news and info Results in 0.20426 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
