| Register file regions for a processing system -> Monitor Keywords |
|
|
  Register file regions for a processing systemUSPTO Application #: 20080022069Title: Register file regions for a processing system Abstract: According to some embodiments, a dynamic region in a register file may be defined for an operand. The defined region may, for example, store multiple data elements, each data element being associated with an execution channel of an execution engine. Information may then be stored into and/or retrieved from the register file in accordance with the defined region. (end of abstract) Agent: Buckley, Maschoff & Talwalkar LLC - New Canaan, CT, US Inventors: Hong Jiang, Val Cook USPTO Applicaton #: 20080022069 - Class: 712022000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Architecture, Array Processor, Array Processor Operation, Single Instruction, Multiple Data (simd) The Patent Description & Claims data below is from USPTO Patent Application 20080022069. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a continuation patent based on, and claiming priority to, the non-provisional patent application filed Dec. 28, 2004, having application Ser. No. 11/024,298 and entitled Register File Regions For A Processing System, the contents of all of which are herein incorporated by reference for all purposes. BACKGROUND [0002] To improve the performance of a processing system, a Single Instruction, Multiple Data (SIMD) instruction is simultaneously executed for multiple operands of data in a single instruction period. For example, an eight-channel SIMD execution engine might simultaneously execute an instruction for eight 32-bit operands of data, each operand being mapped to a unique compute channel of the SIMD execution engine. Moreover, one or more registers in a register file may be used by SIMD instructions, and each register may have fixed locations associated with execution channels (e.g., a number of eight-word registers could be provided for an eight-channel SIMD execution engine, each word in a register being assigned to a different execution channel). An ability to efficiently and flexibly access register information in different ways may further improve the performance of a SIMD execution engine. BRIEF DESCRIPTION OF THE DRAWINGS [0003] FIGS. 1 and 2 are block diagrams of processing systems. [0004] FIG. 3 illustrates an instruction and a register file for a processing system. [0005] FIG. 4 is a flow chart of a method according to some embodiments. [0006] FIG. 5 illustrates an instruction and a register file for a processing system according to some embodiments. [0007] FIG. 6 illustrates execution channel mapping in a register file according to some embodiments. [0008] FIG. 7 illustrates a region description including a horizontal stride according to some embodiments. [0009] FIG. 8 illustrates a region description including a horizontal stride of zero according to some embodiments. [0010] FIG. 9 illustrates a region description for word type data elements according to some embodiments. [0011] FIG. 10 illustrates a region description including a vertical stride according to some embodiments. [0012] FIG. 11 illustrates a region description including a vertical stride of zero according to some embodiments. [0013] FIG. 12 illustrates a region description according to some embodiments. [0014] FIG. 13 illustrates a region description wherein both the horizontal and vertical strides are zero according to some embodiments. [0015] FIG. 14 illustrates region descriptions according to some embodiments. [0016] FIG. 15 is a block diagram of a system according to some embodiments. DETAILED DESCRIPTION [0017] Some embodiments described herein are associated with a "processing system." As used herein, the phrase "processing system" may refer to any device that processes data. A processing system may, for example, be associated with a graphics engine that processes graphics data and/or other types of media information. In some cases, the performance of a processing system may be improved with the use of a SIMD execution engine. For example, a SIMD execution engine might simultaneously execute a single floating point SIMD instruction for multiple channels of data (e.g., to accelerate the transformation and/or rendering three-dimensional geometric shapes). Other examples of processing systems include a Central Processing Unit (CPU) and a Digital Signal Processor (DSP). [0018] FIG. 1 illustrates one type of processing system 100 that includes a SIMD execution engine 110. In this case, the execution engine 110 receives an instruction (e.g., from an instruction memory unit) along with a four-component data vector (e.g., vector components X, Y, Z, and W, each having bits, laid out for processing on corresponding channels 0 through 3 of the SIMD execution engine 110). The engine 110 may then simultaneously execute the instruction for all of the components in the vector. Such an approach is called a "horizontal," "channel-parallel," or "Array Of Structures (AOS)" implementation. [0019] FIG. 2 illustrates another type of processing system 200 that includes a SIMD execution engine 210. In this case, the execution engine 210 receives an instruction along with four operands of data, where each operand is associated with a different vector (e.g., the four X components from vectors V0 through V3). Each vector may include, for example, three location values (e.g., X, Y, and Z) associated with a three-dimensional graphics location. The engine 210 may then simultaneously execute the instruction for all of the operands in a single instruction period. Such an approach is called a "vertical," "channel-serial," or "Structure Of Arrays (SOA)" implementation. Although some embodiments described herein are associated with a four and eight channel SIMD execution engines, note that a SIMD execution engine could have any number of channels more than one (e.g., embodiments might be associated with a thirty-two channel execution engine). [0020] FIG. 3 illustrates a processing system 300 with an eight-channel SIMD execution engine 310. The execution engine 310 may include an eight-byte register file 320, such as an on-chip General Register File (GRF), that can be accessed using assembly language and/or machine code instructions. In particular, the register file 320 in FIG. 3 includes five registers (R0 through R4) and the execution engine 310 is executing the following hardware instruction: [0021] add(8) R1 R3 R4 The "(8)" indicates that the instruction will be executed on operands for all eight execution channels. The "R1" is a destination operand (DEST), and "R3" and "R4" are source operands (SRC0 and SRC1, respectively). Thus, each of the eight single-byte data elements in R4 will be added to corresponding data elements in R3. The eight results are then stored in R1. In particular, the first byte of R4 will be added to the first byte of R3 and that result will be stored in the first byte of R1. Similarly, the second byte of R4 will be added to the second byte of R3 and that result will be stored in the second byte of R1, etc. Continue reading... Full patent description for Register file regions for a processing system Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Register file regions for a processing system patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Register file regions for a processing system or other areas of interest. ### Previous Patent Application: Leverage guest logical to physical translation for host-side memory access Next Patent Application: Programmable image readout sequencer Industry Class: Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors) ### FreshPatents.com Support Thank you for viewing the Register file regions for a processing system patent info. IP-related news and info Results in 1.37128 seconds Other interesting Feshpatents.com categories: Daimler Chrysler , DirecTV , Exxonmobil Chemical Company , Goodyear , Intel , Kyocera Wireless , |
||
