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  Reduction of dopant loss in a gate structureUSPTO Application #: 20070284608Title: Reduction of dopant loss in a gate structure Abstract: A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate. (end of abstract)
Agent: Texas Instruments Incorporated - Dallas, TX, US Inventors: Yuanning Chen, Mark Visokay USPTO Applicaton #: 20070284608 - Class: 257107000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Regenerative Type Switching Device (e.g., Scr, Comfet, Thyristor) The Patent Description & Claims data below is from USPTO Patent Application 20070284608. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a divisional of application Ser. No. 10/681,399, filed Oct. 08, 2003. TECHNICAL FIELD [0002] The present invention relates generally to processes for the manufacture of semiconductor devices and, more particularly, to the formation of nitride spacers for a gate electrode. BACKGROUND OF THE INVENTION [0003] As feature sizes of metal-oxide-semiconductor (MOS) and complementary metal-oxide-semiconductor (CMOS) devices are reduced, the lateral electric field generated in MOS devices increases. A strong enough electric field gives rise to so-called "hot-carrier" effects in MOS devices. Hot-carrier effects cause unacceptable performance degradation particularly in MOS devices with short channel lengths, e.g., less than 0.5 .mu.m. To overcome the hot carrier instability problems of MOS devices, MOS devices can be provided with shallow lightly doped source/drain regions that extend just to the gate electrode region and heavily doped source/drain regions that are laterally displaced away from the gate electrode region. [0004] The lightly doped regions are used to absorb some of the potential into the drain and thus reduce the electric field. The field is reduced by the lightly doped regions because the voltage drop is shared by the drain and the channel, in contrast to a conventional drain structure, in which almost the entire voltage drop occurs across the channel region. The reduction of the electric field causes a reduction in hot carriers injected into a gate dielectric, which greatly increases the stability of the device. [0005] The lightly doped source/drain regions are typically formed in the semiconductor substrate using the gate electrode and sidewall spacers as a mask during the lightly doped source/drain implantation. The sidewall spacers can be formed alongside the gate after the lightly doped source/drain implantation. The heavily doped regions can then be formed in the semiconductor substrate using the gate electrode and additional sidewall spacers laterally displaced from the gate electrode as a mask during the heavy dose source/drain implantation. [0006] The sidewall spacers, which are used in the formation of the lightly doped regions, can be formed from materials, such as silicon nitride and silicon dioxide. Silicon nitride spacers are typically formed by first providing an oxide layer over the gate. The oxide layer functions as an etch stop during formation of the silicon nitride spacers. The oxide layer is typically provided by thermal oxidation processes, such as rapid temperature processing (RTP). A nitride conformal film can then be deposited over the gate, and the nitride film can be anisotropically etched by an etching process, such as plasma etching. [0007] The thermal oxidation process used to form the oxide layer can potentially cause dopant migration or other unwanted effects in surrounding device areas. Dopant migration from the gate to the oxide layer can deplete dopant ions from the gate, which can adversely affect the electrical performance of the MOS device. For example, a MOS device in which dopant ions are depleted from the gate can have a higher resistance, lower carrier concentration, and lower drive current compared to a MOS device in which the dopant ions are not depleted from the gate. SUMMARY OF THE INVENTION [0008] The present invention relates generally to a semiconductor device and to a fabrication method for the semiconductor device (e.g., a MOS field effect transistor (MOSFET) of a flash memory). The semiconductor device can include offset spacers that contact opposing side surfaces of a gate of a gate structure. The gate can be doped and include a top surface that interconnects the opposing side surfaces. A poly re-oxide can be formed by selectively depositing (e.g., physical vapor deposition (PVD)) an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate. The offset spacers can mitigate dopant loss and poly-depletion that could potentially occur from the opposing side surfaces of the gate and improve the operation performance of the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS [0009] The foregoing and other aspects of the present invention will become apparent to those skilled in the art to which the present invention relates upon reading the following description with reference to the accompanying drawings. [0010] FIG. 1 illustrates a schematic cross-sectional view of a MOS structure in accordance with an aspect of the invention. [0011] FIG. 2 illustrates a schematic cross-sectional view of a substrate with an n-well. [0012] FIG. 3 illustrates a schematic cross-sectional view of the n-well of FIG. 2 after a dielectric layer has been formed over the n-well [0013] FIG. 4 illustrates a schematic cross-sectional view of the n-well of FIG. 3 after a conductive layer has been deposited over the dielectric layer. [0014] FIG. 5 illustrates a schematic cross-sectional view of the structure of FIG. 4 after a mask has been formed over the conductive layer. [0015] FIG. 6 illustrates a schematic cross-sectional view of the structure of FIG. 5 after an etching process has been initiated. [0016] FIG. 7A illustrates a schematic cross-sectional view of the structure FIG. 6 after a poly re-oxide layer has been deposited. [0017] FIGS. 7B, 7C, 7D, and 7E illustrate, respectively, apparatuses for depositing the etch stop layer of FIG. 7A. [0018] FIG. 8 illustrates a schematic cross-sectional view of the structure of FIG. 7A after a nitride layer has been deposited. [0019] FIG. 9 illustrates a schematic cross-sectional view of the structure of FIG. 8 after nitride offset spacers have been formed. [0020] FIG. 10 illustrates a schematic cross-sectional view of the structure of FIG. 9 undergoing implantation of an LDD implant. Continue reading... Full patent description for Reduction of dopant loss in a gate structure Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Reduction of dopant loss in a gate structure patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Reduction of dopant loss in a gate structure or other areas of interest. ### Previous Patent Application: Semiconductor light emitting device including porous layer Next Patent Application: Method and apparatus for drain pump power conservation Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Reduction of dopant loss in a gate structure patent info. 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