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Reducing time to design integrated circuits including performing electro-migration checkRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or Evaluating, Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width)Reducing time to design integrated circuits including performing electro-migration check description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070079264, Reducing time to design integrated circuits including performing electro-migration check. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to computer aided design (CAD) of integrated circuits, and more specifically to a method and apparatus for reducing the time to design an integrated circuit (IC) including performing electro-migration check. [0003] 2. Related Art [0004] Integrated circuits are generally designed in multiple stages. For example, a high level design (e.g., in VHDL or Verilog languages, well known in the relevant arts) of an integrated circuit (IC) is synthesized (in a logic synthesis stage) to generate corresponding netlists (containing cells, interconnection details and power supply information). The cells are then placed in a placement stage. [0005] The connections may then be performed first in a global routing stage (in which connections are established ignoring overlap type details) and then a detailed routing stage (in which the connections are routed through various metal layers to avoid overlap as well as to meet other design constraints). All these stages are often performed using corresponding design tools, potentially provided from different vendors (e.g., Cadence, Synopsis). [0006] One of the tasks in such circuit design is electro-migration (EM) check. EM generally refers to dislodging of ions from a metal wire (connecting nodes in an IC), and is caused by current density (current flow divided by width of the metal) exceeding a corresponding threshold. EM impedes the ability of metal to conduct, in addition to leading to reduced life-time. Accordingly, it is generally desirable to ensure that current density does not exceed a desired threshold at least for a substantial amount of time. The related checks in design of ICs may be referred to as EM check. [0007] In one prior embodiment, the EM checks are performed after the detailed routing stage noted above. One advantage of such an approach is that various details such as width (and other geometrical information) of paths (generally referred to as nets in the relevant arts) and expected current strength on the paths would readily be available after the detailed routing stage, and EM check can be easily performed. If a EM violation is detected for a path, the designer is often forced to perform tasks such as increasing the width of the path. [0008] Such an approach may present several disadvantages. For example, increasing the path width can lead to violation of other constraints (e.g., cross-talk noise violation, congestion). Such additional problems may force the designers to revisit at least some of the stages iteratively. For example, a designer may manually attempt to re-route the path. If such re-routing cannot be performed, the designer may need to revisit the earlier design stages (e.g., placement). Such iterative approaches lead to increased design cycle time and costs, and is therefore undesirable at least in some environments. [0009] What is therefore needed is a method and apparatus for reducing the time to design an integrated circuit (IC) including performing electro-migration check. BRIEF DESCRIPTION OF THE DRAWINGS [0010] Various features of the present invention are described with reference to the following accompanying drawings, which are briefly described below. [0011] FIG. 1 is a block diagram of an example system in which various aspects of the present invention can be implemented. [0012] FIG. 2 is a block diagram illustrating the manner in which EM violations are addressed in one prior embodiment. [0013] FIG. 3 is a flow-chart illustrating the manner in which EM violations are addressed in an embodiment of the present of the present invention. [0014] FIG. 4 is a block diagram illustrating the manner in which various early stages can avoid EM violations in an embodiment of the present invention. [0015] FIGS. 5A and 5B are block diagrams together illustrating an approach to avoiding EM violations in one embodiment. [0016] In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [0017] 1. Overview [0018] An aspect of the present invention computes a load limit on each path of an integrated circuit, which would avoid EM violations based on pre-specified values for parameters such as width for the path, and provides as input the load limits to stages earlier than or equal to detailed routing stage (hereafter "early stages"). Each of such early stages may ensure that the load limit is not violated, thereby avoiding EM violations, as desired. As a result, designers may not need to revisit earlier stages for addressing EM violations. The design cycle time and costs may be reduced as a result. [0019] Several aspects of the invention are described below with reference to examples for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide a full understanding of the invention. One skilled in the relevant art, however, will readily recognize that the invention can be practiced without one or more of the specific details, or with other methods, etc. In other instances, well-known structures or operations are not shown in detail to avoid obscuring the invention. [0020] 2. Computer System [0021] FIG. 1 is a block diagram of computer system 100 illustrating an example system in which various aspects of the present invention. The system may be implement a design tool which facilitates design of integrated circuits according to various aspects of the present invention. While the description is provided with respect to a single system merely for illustration, it should be understood that the features can be implemented using several systems, as would typically be the case in the design of complex integrated circuits. Such computer systems are often networked to distribute the various tasks in design of a target integrated circuit. Continue reading about Reducing time to design integrated circuits including performing electro-migration check... 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