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  Reducing nitrogen concentration with in-situ steam generationUSPTO Application #: 20070205446Title: Reducing nitrogen concentration with in-situ steam generation Abstract: In-situ steam generation (ISSG) is used to reduce the nitrogen concentration in silicon and silicon oxide areas. (end of abstract) Agent: Macpherson Kwok Chen & Heid LLP - San Jose, CA, US Inventors: Zhong Dong, Chiliang Chen, Ching-Hwa Chen USPTO Applicaton #: 20070205446 - Class: 257288000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode) The Patent Description & Claims data below is from USPTO Patent Application 20070205446. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] The present application is a division of U.S. patent application Ser. No. 11/365,013 filed on Mar. 1, 2006, incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] The present invention relates to fabrication of integrated circuits, and more particularly to use of in-situ steam generation (ISSG) to form silicon oxide on regions containing silicon and/or silicon oxide and also containing nitrogen. [0003] Nitrogen has been introduced into MOS transistors' gate dielectrics formed of silicon dioxide because nitrogen impedes boron and phosphorus diffusing between the transistor's gate and the channel and source/drain regions. See e.g. U.S. patent application published as no. 2001/0003381 on Jun. 14, 2001, filed by Orlowski et al., incorporated herein by reference. The nitrogen presence is not always desirable, however, because nitrogen can cause degradation of the transistor's performance (due to an increased oxide charge for example). U.S. Pat. No. 6,143,608, issued Nov. 7, 2000 to He et al. describes flash memory fabrication processes in which the gate oxide for the memory cell transistors is formed before the gate oxide for the peripheral transistors. The gate oxide for the memory cell transistors is nitrided, and the nitrogen contaminates the silicon substrate in the peripheral areas. When the peripheral areas are later oxidized to form the gate oxide for the peripheral transistors, the nitrogen slows down the oxidation process and also makes the peripheral gate oxide thickness unpredictable. In addition, the nitrogen undesirably reduces the peripheral transistors' breakdown voltages. The U.S. Pat. No. 6,143,608 therefore proposes to mask the peripheral areas with silicon nitride during the nitridation of the gate oxide of the memory cell transistors. Another solution is to etch away the nitrogen-contaminated silicon region in the periphery before growing the gate oxide for the peripheral transistors. SUMMARY [0004] This section summarizes some features of the invention. Other features are described in the subsequent sections. The invention is defined by the appended claims which are incorporated into this section by reference. [0005] The inventor has discovered that when silicon oxide is grown on a silicon region containing nitrogen by in-situ steam generation (ISSG), the nitrogen concentration can be reduced and predictable silicon oxide thickness can be provided. Moreover, the silicon oxide thickness is not highly dependent on the initial nitrogen concentration. Therefore, in some embodiments, ISSG makes it unnecessary to mask the peripheral areas or to etch away the silicon portion contaminated with nitrogen. [0006] The inventor has also discovered that similar benefits are obtained when ISSG is used to increase the thickness of a silicon oxide layer contaminated with nitrogen. [0007] It is believed that the nitrogen removal can be enhanced by adding diluent gasses (e.g. argon) in the ISSG process. [0008] The invention is not limited to the features and advantages described above. Other features are described below. The invention is defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG. 1 is a block diagram of an ISSG processing chamber suitable for some embodiments of the present invention. [0010] FIG. 2 illustrates forming silicon oxide on a silicon region containing nitrogen. [0011] FIG. 3 is a chart illustrating the silicon oxide thickness as a function of the initial nitrogen concentration when the procedure of FIG. 2 is implemented by ISSG or Rapid Thermal Oxidation (RTO). [0012] FIG. 4 illustrates forming additional silicon oxide on a silicon oxide region containing nitrogen. [0013] FIG. 5 is a chart illustrating the silicon oxide thickness as a function of the initial nitrogen concentration when the procedure of FIG. 4 is implemented by ISSG or Rapid Thermal Oxidation (RTO). [0014] FIGS. 6-9 are graphs showing nitrogen concentration at different depths for at different stages of integrated circuit fabrication. [0015] FIGS. 10-18 are vertical cross sections of integrated circuits in the process of fabrication according to some embodiments of the present invention. DESCRIPTION OF SOME EMBODIMENTS [0016] The embodiments described in this section illustrate but do not limit the invention. The invention is defined by the appended claims. [0017] FIG. 1 illustrates a conventional ISSG chamber 104, such as described in U.S. patent application published as no. 2002/0146914 A1 on Oct. 10, 2002, filed by Huang et al., incorporated herein by reference. A silicon wafer 110 is placed in the chamber heated by a heater 130. Hydrogen, oxygen, and possibly other gases (e.g. argon or helium) are flown into the chamber. Hydrogen reacts with oxygen to form water vapor, i.e. H.sub.2O. The water vapor oxidizes silicon to form silicon dioxide (SiO.sub.2) and hydrogen. The gaseous by-products are pumped out via an exhaust path 144. [0018] In FIG. 2, reference number 210 marks the silicon wafer 140 before the ISSG processing. The wafer contains a silicon substrate 220 (possibly, but not necessarily, monocrystalline silicon). The top region 230 of substrate 220 contains possibly unbound nitrogen atoms. Number 230 marks the wafer after the ISSG processing. The ISSG processing results in formation of silicon dioxide layer 240 on region 220. The nitrogen concentration in region 230 is reduced. [0019] FIG. 3 is a bar diagram comparing the ISSG processing with RTO for thermal oxidation of wafer 140. In both cases, the initial wafer was as in FIG. 2 at 210. Nitrogen was introduced into region 230 by thermal nitridation using NO and/or N.sub.2O. (Nitrogen can also be introduced by thermal nitridation with NH.sub.3 or by other methods, e.g. decoupled plasma nitridation or remote plasma nitridation or ion implantation, but this was not done in the experiment being described.) The ISSG was performed at 900.degree..about.1100.degree. C. at a pressure of 5.about.15 torr for 20.about.200 seconds. The hydrogen flow was 0.1.about.2.0 liters per minute, the oxygen flow was 3.about.10 liters per minute, the argon flow was 0.about.10 liters per minute. The processing was conducted in a chamber designed for 8-inch wafers. (For a 12-inch wafer, the flow rates may be 30.about.100% higher.) The resulting oxide 240 was about 60.ANG. thick. Four ISSG experiments were performed, with the initial nitrogen concentration in region 230 being respectively 5.20%, 3.50%, 2%, and 0% (atomic percent). The RTO was also performed on four different wafers, with the same initial nitrogen concentrations. The RTO temperature was 950.degree..about.1100.degree. C.; the oxygen flow was 3.about.10 liters per minute; the pressure was 700.about.780 torr; the duration was 20.about.200 seconds. For each nitrogen concentration, the ISSG oxide thickness and the RTO oxide thickness are shown by the adjacent bars in FIG. 3. For the ISSG, the resulting thickness of oxide 240 was about 60 .ANG. regardless of the initial nitrogen concentration. For the RTO, the resulting oxide thickness strongly depended on the initial nitrogen concentration, varying from about 60 .ANG. at zero concentration to below 20 .ANG. for the 5.20% concentration. Continue reading... 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