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Reduced dry etching lagRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects)Reduced dry etching lag description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060199366, Reduced dry etching lag. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD [0001] This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to etching the layers, most specifically silicon dioxide layers, of which integrated circuits are formed. BACKGROUND [0002] Integrated circuits are fabricated by forming a layer, performing some type of processing in regard to that formed layer--such as etching--and then forming an overlying layer. This process is repeated many times until the completed integrated circuit is formed. [0003] As the term is used herein, "integrated circuit" includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices. [0004] One layer type that is commonly used is a dielectric or electrically insulating layer between two electrically conductive layers, such as metal layers. An oxide of some type, most commonly silicon dioxide, is often used to form the dielectric layer. These dielectric layers are used to electrically insulate the adjacent electrically conductive layers one from another. However, it is typically desirable to form a pattern of via holes through the dielectric layer after it is formed, and fill the via holes with an electrically conducting material, such as metal, so that selective electrical connections can be made between the overlying and underlying conductive layers, through the dielectric layers. [0005] Such via holes are typically formed by an etching process of some type. A layer of photoresist is applied to the dielectric layer, and exposed and developed to produce a via hole pattern in the photoresist. The substrate is then subjected to a wet or dry etch, such as a physical ion or reactive ion etching process. The photoresist protects the dielectric layer from etching in those areas where the photoresist layer remains, but where the photoresist layer has been developed away, the dielectric layer etches in the via hole pattern. [0006] Etching preferably continues until all of the via holes in the pattern have been etched to the desired depth. Unfortunately, for a variety of reasons, some of the via holes tend to etch at a different rate than others of the via holes. For example, those via holes that are grouped together in a relatively dense pattern of via holes tend to etch at a rate that is somewhat greater than those via holes that are in a relatively isolated pattern. If the dielectric layer is allowed to etch for a length of time that is sufficient to completely etch the relatively isolated via holes, then the relatively dense via holes tend to be over etched. Conversely, if the dielectric layer is etched for a length of time that is only sufficient to completely etch the relatively dense via holes, then the relatively isolated via holes tend to be under etched. In either case, the operation of the integrated circuit tends to be compromised. [0007] Various etching parameters can be adjusted in order to reduce the difference in etch rate between the relatively dense via holes and the relatively isolated via holes. This difference is sometimes referred to a lag in the etch rate of the relatively isolated via holes. For example, the kind of gas that is used for the dry etching, the gas flow rates, the chamber pressure, the substrate temperature, and the processing power can all be adjusted in order to try to reduce the etch lag. However, these parameters all tend to also effect other characteristics of the etch process, such as the etch rate, etch selectively, and etch profiles, one or more of which may be deleterious to the process. [0008] What is needed, therefore, is a method of etching relatively dense via holes and relatively isolated via holes in a manner that generally reduces problems such as those described above, at least in part. SUMMARY [0009] The above and other needs are met by a method of forming via structures between a first electrically conductive layer and a second electrically conductive layer. The first electrically conductive layer is formed, and a dielectric layer is formed over the first electrically conductive layer. A first photoresist layer is formed over the dielectric layer, and patterned with a first via hole pattern. The first via hole pattern includes via holes that are all disposed within a first distance one from another, called dense via holes, and excludes via holes that are disposed at greater than the first distance one from another, called isolated via holes. The dense via holes are etched into the dielectric layer at first etch conditions until the dense via holes are properly formed, and the first photoresist layer is removed. [0010] A second photoresist layer is formed over the dielectric layer, and is patterned with a second via hole pattern. The second via hole pattern excludes dense via holes and includes isolated via holes. The isolated via holes are etched into the dielectric layer at second etch conditions until the isolated via holes are properly formed, and the second photoresist layer is removed. Electrically conductive vias are formed within both the dense via holes and the isolated via holes, and the second electrically conductive layer is formed over the dielectric layer. Electrical continuity exists between the first electrically conductive layer and the second electrically conductive layer through the electrically conductive vias. [0011] By separating the etch processes for the dense via holes and the isolated via holes in this manner, the etch conditions can be adjusted as necessary so that both the dense via holes and the isolated are properly formed. In addition, adjustment of etch conditions that would adversely effect other etch parameters can be avoided in both of the etch processes. For example, in one embodiment, only the length of time is varied between the two etch processes. Although the method requires an additional masking step, the improvement in the etch of the via holes tends to make the additional processing worthwhile. In some embodiments, more than two mask levels are used to etch all of the vias, by dividing the via holes into more than two groups, such as a dense group, an intermediate group, and an isolated group. Any number of groups, all preferably based on via hole density, could be used, as desired. The various groups could be etched in any order desired, and the most dense group need not be etched prior to the other group or groups. [0012] In various embodiments, the first etch conditions are different from the second etch conditions. In some embodiments, the dense via holes and the isolated via holes all have a diameter of no more than about two hundred nanometers. In different embodiments, the etches are one or more of a reactive ion etch, a physical etch, and a wet etch. BRIEF DESCRIPTION OF THE DRAWINGS [0013] Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein: [0014] FIG. 1 is a cross sectional view of a portion of an integrated circuit depicting a substrate, a lower electrically conductive layer, a dielectric layer in which via holes are to be formed, and a first photoresist layer patterned with a first via hole pattern for dense via holes. [0015] FIG. 2 is a cross sectional view of the integrated circuit of FIG. 1, where the dense via holes have been etched and the first photoresist layer has been removed. [0016] FIG. 3 is a cross sectional view of the integrated circuit of FIG. 2, where a second photoresist layer has been applied and patterned with a second via hole pattern for isolated via holes. [0017] FIG. 4 is a cross sectional view of the integrated circuit of FIG. 3, where the isolated via holes have been etched and the second photoresist layer has been removed. [0018] FIG. 5 is a cross sectional view of the integrated circuit of FIG. 4, where the via holes have been filled and an upper electrically conductive layer has been formed. DETAILED DESCRIPTION [0019] With reference now to FIG. 1, there is depicted a cross sectional view of a portion of an integrated circuit 10 with a substrate 12, a lower electrically conductive layer 14, a dielectric layer 16 in which via holes are to be formed, and a first photoresist layer 18 patterned with a first via hole pattern 20 for dense via holes 22. Continue reading about Reduced dry etching lag... Full patent description for Reduced dry etching lag Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Reduced dry etching lag patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Reduced dry etching lag or other areas of interest. ### Previous Patent Application: Junction-isolated vias Next Patent Application: Semiconductor device and manufacturing method thereof Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Reduced dry etching lag patent info. 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