| Recording medium recording a wiring method -> Monitor Keywords |
|
|
 
Recording medium recording a wiring methodRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Routing (e.g., Routing Map, Netlisting), Global Routing (e.g., Shortest Path, Dead Space, Or Duplicate Trace Elimination)Recording medium recording a wiring method description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060156267, Recording medium recording a wiring method. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS [0001] This application is a division of application Ser. No. 10/808,530, filed Mar. 25, 2004, now pending, which is a division of application Ser. No. 09/739,826, filed Dec. 20, 2000, now U.S. Pat. No. 6,732,345, issued May 4, 2004, and based on Japanese Patent Application No. 11-363393, filed Dec. 21, 1999, by Toshikazu KATO. This application claims only subject matter disclosed in the parent application and therefore presents no new matter. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a layout and wiring system and a wiring method for use in the automatic layout and wiring system, and more particularly, to a layout and wiring system and a wiring method for use in the automatic layout and wiring system, capable of wiring electronic components in accordance with a short-run rule which partially allows a wiring space smaller than the wiring minimum space according to a design rule only if a predetermined condition is fulfilled, and a recording medium which records the wiring method for use in the automatic layout and wiring system. [0004] 2. Description of the Related Art [0005] In an LSI (Large-Scale Integration) layout design, art-work data regarding the wiring in the entire chip is created based on data regarding the wiring in a library. The creation of such art-work data is performed based on the chip size and a circuitry diagram which are shown in the unit of logical functions (blocks) a collection of which are prepared as a library. The creation of such art-work data is performed using an automatic layout and wiring system as a CAD (Computer Aided Design) system. Along with the large scale and rapid development in the integration of the LSI chips in recent years, a higher degree of integration in automatic layout in automatic layout and wiring systems is desired. Hence, it is demanded that automatic layout and wiring systems include a wiring function for wiring a number of wiring layers and be able to wire electronic components even if a number of vias for connecting the wiring layers are included. [0006] The structure of the conventionally-used automatic layout system and a process for automatically layout and wiring electronic components will now schematically be explained. FIG. 11 is a diagram showing the structure of the automatic layout and wiring system. In the automatic layout and wiring system 1, reading/previous-processing means 6 is prepared for: (1) reading information regarding the connection made between terminals of each block forming an LSI to be designed from a circuitry diagram information file 2; (2) reading art-work data regarding cells/blocks for use in the LSI to be designed, from information regarding vias or cells such as a NAND gate, etc. and registered in a cell/block library 3, and/or information including any blocks for realizing complicated logical functions; (3) and reading, from a design rule file 4, a design rule for wiring electronic components under some conditions, such as a wiring pitch between wiring layers, the wiring width, the wiring minimum space, and the size of each element forming a via cell, and for inspecting the above conditions. On the basis of the read information, main automatic layout and wiring means 7 creates data for laying out and wiring the cells/blocks, and carries out the process for laying out and wiring the cells/blocks. Resultant layout and wiring inspection means 8 inspects the resultant layout and wiring performed by the main automatic layout and wiring means 7. If there is no defect in the resultant wiring which has undergone the inspection, the data regarding the resultant wiring is re-converted into art-work data. Thereafter, the art-work data is output from the automatic layout and wiring system 1 to a layout and wiring result output file 5. On the contrary, if a defect is found during the inspection, the defect is corrected, and the process for laying out and wiring the cells/blocks is carried out again, by inputting/editing means (not illustrated) which is included in the automatic layout and wiring system 1. [0007] FIG. 12 is a flow diagram for explaining the entire process for laying out and wiring electronic components. In a process 121 for reading a library, the automatic layout and wiring system reads out circuitry information, the wiring pitch, the wiring width, the wiring minimum space, the side length of each via, and information regarding blocks to be arrayed. Such information are registered in advance as library data in the circuitry diagram information file 2, the cell/block library 3, the design rule file 4. Further, the automatic layout and wiring system sets a rule for laying out and wiring the electronic components. In a process 122 for laying out cells/blocks, the primitive cells and the logical functional blocks, which are illustrated in the circuitry diagram, are automatically laid out in an LSI chip. In a process 123, for wiring cells/blocks, terminals between cells/blocks are automatically wired in accordance with a set rule. In a process 124, for inspecting wired cells/blocks, the electronic components are inspected as to whether there is an un-laid block, any unconnected portion of wiring, and whether there is a shorted circuit. In a process 125 for outputting data regarding the laid out and wired cells/blocks, data for the automatic layout and wiring system is converted into art-work data corresponding each wiring pattern forming an LSI, and the converted data is output to the layout and wiring result output file 5. Then, the entire process for laying out and wiring the electronic components is completed. [0008] FIG. 13 is a flow diagram for specifically explaining the process 121, which is included in the entire process for laying out and wiring electronic components shown in FIG. 12. The conventional process 121 includes a process 131, for reading out circuitry diagram information from the circuitry diagram information file 2 and writing the read information into the automatic layout and wiring system, a process 132, for reading design rule information from the design rule file 14, and a process 133 for reading information regarding any cells/blocks for use in laying out and wiring the electronic components from the cell/block library 3. [0009] The process 132, includes steps 134, 135, 136, 137 and 138. The step 134 is prepared for reading a wiring pitch P indicating a space between grid lines in the wiring. The step 135 is prepared for reading a wiring width W which is a standard level for signal wiring. The step 136 is prepared for reading the wiring minimum space S which is the allowable minimum value for a space between a portion of wiring and another portion of wiring. The step 137 is prepared for reading a side length V of a via in a via cell. The step 138 is prepared for reading a via margin M. [0010] FIG. 14A is a planer view of a via cell, and FIG. 14B is a cross sectional view exemplarily showing a via cell included in an LSI. In a via cell 23 shown in FIG. 14A, a via 141 for connecting upper wiring with lower wiring is formed in a square shape having a side length V. As shown in FIG. 14B, a lower wiring layer 22a and an upper wiring layer 21a are larger in width than the wire by via margins M, which is prepared on all sides of the via 141, than the via 141. In this structure, the via 141 does not extend beyond the upper wiring layer 21 and the lower wiring layer 22a, even if the positional deviation occurs between the via and the lower wiring layer pattern and/or between the via and the upper wiring layer pattern in a lithography process during the LSI manufacture. A reference numeral 142 denotes an insulation layer such as a silicon oxide film, etc. [0011] As shown in FIG. 13, the process 133 includes a step 139 of reading an art-work cell name of the via cell 23, and a step 140 of reading information regarding any cells/blocks for use in laying out and wiring the electronic components. [0012] FIGS. 15A and 15B are diagrams each exemplarily showing output art-work data of wiring according to a conventional wiring method. As shown in the first conventional wiring method of FIG. 15A, based on its design rule, there are several conditions that a wiring pitch P=1.00 .mu.m, a wiring width W=0.50 .mu.m, the wiring minimum space S=0.50 .mu.m, a side length of each via V=0.50 .mu.m, and a via margin M=0.05 .mu.m. The wiring space between portions of wiring, extending along grid lines which are parallel and adjacent to each other, is equal to 0.50 .mu.m, i.e. (P-W)=0.50 .mu.m. This satisfies above condition that the wiring minimum space S=0.50 .mu.m. However, the space between a via cell and a portion of wiring respectively on adjacent and parallel grid lines is equal to 0.45 .mu.m, i.e. (P-V-M)=0.45 .mu.m, and the space between a via cell and another via cell respectively on adjacent and parallel grid lines is equal to 0.40 .mu.m, i.e. (P-V-M-M)=0.40 .mu.m. Both of the spaces do not fulfill the above condition that the wiring minimum space S=0.50 .mu.m. Under the consideration of this, as illustrated in FIG. 15A, each via cell 23 needs to be arranged with a space of 1 pitch away from another portion of wiring 21 or another via cell 23. Hence, in this conventional wiring method, the occupied area A=15.00 .mu.m.sup.2. The larger the number of via cells, the larger the occupied area. A reference numeral 21 denotes an upper wiring layer, whereas a reference numeral 22 denotes a lower wiring layer. [0013] In the second conventional wiring method of FIG. 15B, the wiring pitch P(V+M+M+S)=1.10 .mu.m, so that the wiring space between via cells which are arranged respectively on adjacent and parallel grid lines is equal to or larger than the wiring minimum space S. According to this method, the occupied area A=10.89 .mu.m.sup.2. In such a structure, because the wiring pitch P=1.10 .mu.m between target wiring layers over the entire LSI, if the number of via cells is small, the occupied area may increase as compared with the first conventional wiring method of FIG. 15A. [0014] FIG. 16 is a flow diagram showing a process for replacing a via cell(s), according to the third conventional wiring method which is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. H3-29343. The entire contents of this publication is herein incorporated by reference in its entirety. A process 160, for replacing a via cell, is carried out after the process 123 and before the process 124. In this third conventional wiring method, as shown in FIG. 17, a plurality of via cells 171 and 172 are prepared. Of the plurality of via cells 171 and 172 of various origins, a via cell with an adequate origin is selected, and any via cell(s) of an inappropriate origin is(are) replaced with the selected via cell. [0015] As shown in FIG. 16, the process 160 includes steps 161, 162, 163, 164, 165 and 166. Data regarding laid out and wired electronic components is read out in the step 161. Information regarding the plurality of via cells of various origins is read out in the step 162. The wiring state of each portion of wiring, where a corresponding via cell is arranged, is identified in the step 163. The origin of each via cell is identified in the step 164. In the step 165, as shown in the third conventional wiring method of FIG. 17, a via cell of an adequate origin is selected. At the same time, each via is set small to the extent that the space between each via cell and a portion of wiring, along a grid line which is parallel and adjacent to a grid line of the via cell, and that the space between via cells are equal to or larger than the wiring minimum space S. In the step 166, any via cell(s) of an inadequate origin is replaced with the selected via cell. [0016] After the step 160 is completely carried out, the via cells 171 and 172 of various origins are laid out as shown in FIG. 17. According to the third conventional wiring method, the wiring patterns, wherein the wiring pitch P=1.00 .mu.m and the occupied area A=12.00 .mu.m.sup.2, can be realized. In the third conventional wiring method, the occupied area can surely be smaller than that of the first conventional wiring method. In addition, the third conventional wiring method is more effective than the second conventional wiring method, if a small number of via cells are used. However, in recent products of LSIs which are quite large in scale, millions of via cells are included. In this structure, more than ten hours of processing time is required for selecting a via cell of an adequate origin from the number of via cells of four or five various origins. [0017] According to the conventional wiring methods, the allowable wiring space must be equal to or larger than the wiring minimum space S. However, recently, as long as the wiring space is equal to or smaller than a limit value of a predetermined wiring-facing length SL, the wiring space can be smaller than the wiring minimum value unless the wiring space is not further smaller than a short-run wiring space SS. This is called a short-run rule which is employed in the recent LSI manufacture. In the main automatic layout and wiring means 7 shown in FIG. 11, there is no function for wiring electronic components appropriately in consideration of the limit values of the wiring minimum space S and the short-run space SS. Further, the wiring has to be performed in consideration of only the wiring minimum space S which is larger than the short-run space SS as the limit value. Therefore, the occupied area is determined only according to the first, second, and third conventional wiring methods. Hence, while the wiring is performed by the automatic layout and wiring system, it is difficult to reduce the occupied area of the LSI chips because the effective use of the short-run rule is can not easily be realized. SUMMARY OF THE INVENTION [0018] It is accordingly an object of the present invention to provide a wiring method for use in an automatic layout and wiring system, which can effectively employ a short-run rule for performing a wiring process and can realize a decrease in an occupied area of LSI chips. [0019] In order to achieve the above object, according to the first aspect of the present invention, there is provided a wiring method for use in an automatic layout and wiring system which automatically performs laying out and wiring of electronic components in a grid having a plurality of grid lines set at a predetermined wiring pitch, the method comprising: [0020] detecting whether a wiring space, between a wiring layer pattern of a via cell and a wiring layer pattern along a grid line which is parallel and adjacent to a grid line of the via cell, is equal to or larger than a short-run wiring space, and creating, when detected that the wiring space is equal to or larger than the short-run wiring space, via cell data including a via margin which is set in such a way that a wiring space between the parallel grid lines of the via cell is equal to or larger than a wiring minimum space (which is long), the via cell being registered in a library and including a via with a square shape, an upper wiring layer and a lower wiring layer both covering the via and extending by the via margin in all directions; and [0021] performing laying out and wiring of the electronic components using the via cell data, and replacing the via cell data with art-work data corresponding to the via cell. [0022] In the above method, there may be included a process for reading information including circuitry diagram information, a design rule, a cell/block library prior to the layout and wiring of the electronic components. This process may include a process for adapting a short-run rule. In the process for adapting a short-run rule, determination is made as to whether a wiring space between portions of via cells respectively along parallel and adjacent grids is equal to or larger than a short-run wiring space, when the length of the portions is within a limit value of a predetermined wiring-facing length. Further, in the process for adapting a short-run rule, there may be included a process for creating via-cell data, including a via margin which is so changed that the wiring space between the portions is equal to or larger than the wiring minimum space (which is large), based on the via cells. The process for adapting a short-run rule may include: a step of reading information including the limit value of a predetermined wiring-facing length suitable for the short-run rule and the allowable short-run wiring space; a step of determining that the short-run rule can be adapted when determined that the wiring space is equal to or larger than the short-run wiring space, and setting a via-margin changing flag indicating "change"; and a step of creating via cell data including a via margin which is so changed that the wiring space between the portions of wiring is equal to or larger than the wiring minimum space, based on the via cells, when the via-margin changing flag is set indicating "change" in the step of determining whether to adapt the short-run rule. [0023] According to the second aspect of the present invention, there is provided a wiring method for use in an automatic layout and wiring system which automatically perform layout and wiring of electronic components in a grid having a plurality of grid lines set at a predetermined wiring pitch, the method comprising: [0024] detecting whether a wiring space, between portions of wiring along grid lines respectively having via cells which are parallel and adjacent to each other, is equal to or larger than a short-run wiring space, and creating, when detected that the wiring space is equal to or larger than the short-run wiring space, via cell data including a via margin which is changed based on the via cells in such a way that the wiring space is equal to or larger than a wiring minimum space (long), each of the via cells being registered in a library and including a via with a square shape, an upper wiring layer and a lower wiring layer both covering the via and extending by the via margin in all directions; and [0025] performing layout and wiring of the electronic components using the via cell data, and replacing the via cell data with art-work data corresponding to the via cell. Continue reading about Recording medium recording a wiring method... Full patent description for Recording medium recording a wiring method Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Recording medium recording a wiring method patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Recording medium recording a wiring method or other areas of interest. ### Previous Patent Application: Probabilistic congestion prediction with partial blockages Next Patent Application: Circuit design platform Industry Class: Data processing: design and analysis of circuit or semiconductor mask ### FreshPatents.com Support Thank you for viewing the Recording medium recording a wiring method patent info. IP-related news and info Results in 0.14275 seconds Other interesting Feshpatents.com categories: Electronics: Semiconductor , Audio , Illumination , Connectors , Crypto , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
