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  Reconfigurable circular busUSPTO Application #: 20070019570Title: Reconfigurable circular bus Abstract: A system provides communication between a plurality of cores in an integrated circuit. The system comprises a circular segmented bus operatively connected to each of the cores for transferring data between the plurality of cores. An arbiter arbitrates which of the plurality of cores can transmit data at any given time. (end of abstract)
Agent: Wood, Phillips, Katz, Clark & Mortimer - Chicago, IL, US Inventors: Peter J. Jenkins, Francis A. Kampf USPTO Applicaton #: 20070019570 - Class: 370258000 (USPTO) Related Patent Categories: Multiplex Communications, Network Configuration Determination, In A Bus System, In A Ring System The Patent Description & Claims data below is from USPTO Patent Application 20070019570. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application is a continuation of Utility application Ser. No. 10/063,456, filed Apr. 24, 2002. FIELD OF THE INVENTION [0002] This invention relates to a system for providing communications between cores in an integrated circuit and, more particularly, to a reconfigurable circular bus. BACKGROUND OF THE INVENTION [0003] A typical processing device includes various circuits such as a processor circuit, memory circuits, peripheral circuits, and the like. With recent technology, such a device may be manufactured using a printed circuit board supporting a plurality of integrated circuit chips. Each integrated circuit chip provided the functionality of one or more of the circuits. The individual circuits can be thought of as "core" circuits, or cores. When connected on a printed circuit board, the core circuits are often connected with point to point wiring. [0004] More recently, system-on-a-chip (SOC) technology has been utilized. This technology is used, for example, in large ASICs (application specific integrated circuits) with many cores. The interconnection between cores becomes difficult due to wiring constraints and wiring congestion. A typical bus structure helps alleviate this problem by minimizing the wires between the various cores. Referring to FIG. 1, a block diagram for a typical SOC integrated circuit 10 is illustrated. The illustrative integrated circuit 10 includes six cores 12, 13, 14, 15, 16 and 17. Particularly, the cores 12, 13, 14, 15, 16 and 17 are identified under the letters A, B, C, D, E and F, respectively. Each of the cores 12-17 is connected to a data bus 18 and an address bus 20. This prior art structure limits the amount of bandwidth available for communication between the cores 12-17. All cores 12-17 share the same wires. As a result, only one pair of cores can communicate at the same time. The core connections may be tri-statable, or formed by ORing the gated outputs of all cores into one source driven back to all of the cores. Control of the buses 18 and 20 is granted by an arbiter (not shown) which grants control of the bus to one core at a time. [0005] The present invention is directed to improvements in communication between cores in an integrated circuit. SUMMARY OF THE INVENTION [0006] In accordance with the invention, there is disclosed a system for providing communication between a plurality of cores in an integrated circuit. The system comprises a circular segmented bus operatively connected to each of the cores for transferring data between the plurality of cores. Arbiter means arbitrate which of the plurality of cores can transmit data at any given time. [0007] The circular segmented bus may comprise a data bus, an address bus, both a data bus and an address bus, or another type of bus. [0008] Additionally, the bus may comprise a split transaction data bus and address bus. [0009] The circular segmented bus may comprise a circular bus and isolation means operatively positioned in the circular bus between each pair of adjacent cores. The isolation means may comprise a plurality of transmission gate switches or a plurality of multiplexers. [0010] The arbiter means may be operatively connected to each of the plurality of cores and receive access requests from the cores. The arbiter means may dynamically segment the circular segmented bus responsive to the access request. The arbiter means may dynamically segment the circular segmented bus responsive to the access request and destinations for data and to provide a maximum number of simultaneous transmissions. [0011] Further features and advantages of the invention will be readily apparent from the specification and from the drawing. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 is a block diagram of a prior art system for providing communication between cores in an integrated circuit; [0013] FIG. 2 is a block diagram of a system for providing communication between cores in an integrated circuit in accordance with the invention; [0014] FIG. 3 is a flow diagram illustrating a program implemented by an arbiter/router of FIG. 2; [0015] FIG. 4 is a block diagram, similar to FIG. 2, illustrating a configured circular bus capable of two simultaneous transfer operations; and [0016] FIG. 5 is a block diagram, similar to FIG. 2, illustrating a configured circular bus capable of three simultaneous transfer operations. DETAILED DESCRIPTION OF THE INVENTION [0017] In accordance with the invention, a reconfigurable circular segmented bus is provided which enables more than one pair of cores to share the bus at the same time. The ability to support simultaneous data operations increases the bus bandwidth available to the cores. [0018] Referring to FIG. 2, a block diagram illustrates the interconnections of the reconfigurable circular segmented bus in accordance with the invention. Particularly, an integrated circuit 30 includes six core circuits, or cores, 32, 33, 34, 35, 36 and 37. The cores 32, 33, 34, 35, 36 and 37 are additionally identified with the letters A, B, C, D, E, and F, respectively. The present invention is not intended to be limited to any particular type of core circuits. The cores 32-37 may be configured as bus master devices that initiate an operation. Such core devices may include, for example, a processor, a peripheral device, a DMA controller, or the like. Additionally, some of the cores 32-37 may consist of bus slave devices which responds to operations. Continue reading... Full patent description for Reconfigurable circular bus Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Reconfigurable circular bus patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Reconfigurable circular bus or other areas of interest. ### Previous Patent Application: Methods for automatically selecting a cluster header in a wireless sensor network and for dynamically configuring secure wireless sensor network Next Patent Application: Apparatus and method for audio communications Industry Class: Multiplex communications ### FreshPatents.com Support Thank you for viewing the Reconfigurable circular bus patent info. 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