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  Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the sameUSPTO Application #: 20070090452Title: Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same Abstract: The recess channel transistor includes: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate formed in the recess and a top gate formed on the substrate; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate, where the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. Accordingly, characteristics of the transistor can be prevented from deteriorating due to misalignment of the top gate with the recess gate. (end of abstract)
Agent: Ladas & Parry LLP - Chicago, IL, US Inventors: Gyu Seog Cho, Yong Taik Kim USPTO Applicaton #: 20070090452 - Class: 257330000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Short Channel Insulated Gate Field Effect Transistor, Gate Controls Vertical Charge Flow Portion Of Channel (e.g., Vmos Device), Gate Electrode In Groove The Patent Description & Claims data below is from USPTO Patent Application 20070090452. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the invention [0002] The present invention relates generally to a recess channel transistor, and more particularly to a recess channel transistor and a method of forming the same, which can prevent deterioration of transistor characteristics due to misalignment between a recess gate and a top gate on the recess gate. [0003] 2. Description of the Prior Art [0004] Recently, as the design rule for currently developing semiconductor memory devices reduces the device sizes below sub-100 nm, it has become very difficult to secure sufficient data retention time. When the minimum feature size is reduced, doping density in a substrate must be increased. Thus, if the doping density in the substrate becomes higher, the electric field and the junction leakage must also increase. Therefore, in order to realize a target threshold voltage Vt required by a certain semiconductor memory device, a transistor having an existing planar structure faces a limitation in view of processing and device characteristics. [0005] Accordingly, a recess channel transistor structure extending the channel length has been proposed as a method for decreasing the substrate doping density. Such a recess channel transistor can reduce the substrate doping density, thereby extending the data retention time. Further, such a recess channel transistor can lower the electric field, thereby making it possible to obtain an excellent refreshing characteristic. In addition, as the channel length increases, it is possible to improve characteristics of DIBL and BVds, resulting in the improvement of cell characteristics. [0006] Hereinafter, a conventional method for forming a recess channel transistor, which had been previously proposed, will be described in brief. [0007] First, a recess mask is formed on a semiconductor substrate to expose an activation region in which gates are formed. Then, the exposed activation region of the substrate is etched so as to form recesses. Next, after the recess mask is removed, a gate insulation layer is formed on a bottom surface of each recess. Sequentially, after a gate conductive layer is formed on a whole surface of the substrate in order to fill in the recesses, a hard mask layer is formed on the gate conductive layer. [0008] In turn, the hard mask layer and the gate conductive layer are etched so as to form a gate in each recess. Next, after a Lightly Doped Drain (LDD) ion implant process is performed on the resultant of the substrate, a spacer is formed at both side walls of each gate. Then, source/drain regions are formed at both sides of each gate, including the spacer on the surface of the substrate, thereby establishing the formation of the recess channel transistor. [0009] In the recess channel transistor formed by the method described above, it is important that the two transistors which are formed in a cell have the same shapes. Thus, the gate formed in the recess must be accurately aligned with the top gate integrated with the recess gate. [0010] However, it is substantially difficult to control the alignment of the recess gate with the top gate. Thus, the misalignment of the recess gate with the top gate may occur. It causes a change in the characteristics of the transistor, which thereby fails to obtain desired cell characteristics. [0011] FIG. 1 is a cross-sectional view for illustrating a conventional recess channel transistor. Problems in the conventional transistor will be described in brief. [0012] As shown in FIG. 1, various factors relating to the processes cause the misalignment of the recess gate 104a with the top gate 104b to be integrated with the recess gate. In this case, in view of a storage node, a left transistor differs structurally from a right transistor. This causes both transistors to have different threshold voltage Vt. Thus, the difference in the threshold voltage Vt between both transistors causes a tWR characteristic to be weak when a cell has a relatively high threshold voltage, while causing an Ioff characteristic to be weak when the cell has a relatively low threshold voltage. As a result, it is difficult to store data in the cell. [0013] Further, the misalignment of the recess gate 104a with the top gate 104b causes the recess gate 104a to be subjected to etching damages. Thus, the gate insulation layer 103 at the channel becomes thick, thereby abnormally increasing the threshold voltage so that tREF/tWR characteristics deteriorate. [0014] In FIG. 1, a reference numeral "101" denotes a semiconductor substrate, a reference numeral "102" indicates a device insulation layer, and a reference numeral "105" denotes a hard mask layer. Further, reference numerals "106", "107", and "108" respectively indicate a spacer, a source region in contact with a storage nod, and a drain region in contact with a bit line. SUMMARY OF THE INVENTION [0015] Accordingly, the present invention has been developed in order to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a recess channel transistor and a method for forming the same, which can prevent characteristic of the transistor from deteriorating due to misalignment between a recess gate and a top gate which is arranged on the recess gate. [0016] In order to accomplish the object of the present invention, according to an aspect of the present invention, there is provided a recess channel transistor which comprises: a semiconductor substrate including a device insulation layer defining an activation region in which recesses are formed, gates being formed in the recesses respectively; insulation buffer patterns, each of which is formed at an opening of the recess on a surface of the substrate; gates, each of which includes a recess gate which is formed in the recess and a top gate which is formed on the substrate including the recess gates; spacers, each of which is formed at both sides of the gate; and a source region and a drain region formed at both sides of each gate on the surface of the substrate including the spacer, wherein the source and drain regions have even doping profile due to the existence of insulation buffer patterns. [0017] Here, the insulation buffer patterns are respectively made of a nitride layer or a nitric oxide layer. In addition, the insulation buffer patterns are formed at a depth of 100.about.300 .ANG. on the surface of the substrate and at a width of 50.about.500 .ANG. on a side wall of the recess. The recess gates are formed at a depth of 5001000 .ANG.. [0018] In order to accomplish the object of the present invention, according to another aspect of the present invention, there is provided a method for forming a recess channel transistor, which comprises the steps of: preparing a semiconductor substrate having an activation region and a device insulation region; etching gate forming portions in the activation region of the substrate, so as to form first recesses; etching the device insulation region, so as to form trenches; filling the trenches and the first recesses with an insulation layer; etching center portions of the insulation layer filled in the first recesses and the substrate under the insulation layer, so as to make second recesses deeper than the first recesses and to form the insulation buffer patterns at an opening of the second recesses; forming a gate insulation layer on an inner wall of the second recesses and a surface of the substrate; forming a gate conductive layer on the whole surface of the substrate in order to fill in the second recesses; etching the gate conductive layer, so as to form the gates including the recess gates disposed in the second recesses and the top gates disposed on the recess gates; forming spacers at both sidewalls of each gate; and performing source/drain ion implant on the resultant of the substrate, so as to form a source region and a drain region at both sides of the gates in the surface of the substrate including the spacers, wherein the source and drain regions have an even doping profile due to an existence of insulation buffer patterns. [0019] The first recesses are formed at a depth of 100.about.300 .ANG.. The second recesses are formed at a depth of 500.about.1000 .ANG.. The insulation buffer patterns are formed of a nitride layer or a nitric oxide layer, which are formed at a depth of 100.about.300 .ANG. in the surface of the substrate and at a width of 50.about.500 .ANG. on the inner surface of the second recesses. [0020] The method of the present invention further comprises the steps of: forming a hard mask layer on the gate conductive layer; and etching the hard mask layer, after forming the gate conductive layer and before etching the gate conductive layer. [0021] In order to accomplish the object of the present invention, according to still another aspect of the present invention, there is provided a method for forming a recess channel transistor, which comprises the steps of: preparing a semiconductor substrate including a device insulation layer defining an activation region; etching a gate forming portion in the activation region of the substrate, so as to form first recesses; forming an insulation layer on a whole surface of the substrate including the first recesses; etching the insulation layer in blanket manner, so as to form insulation buffer patterns on a side wall of the first recesses; etching a bottom surface of the first recesses having no insulation buffer pattern, so as to make second recesses deeper than the first recesses; forming a gate insulation layer on a surface of the second recesses and the surface of the substrate; forming a gate conductive layer on the whole surface of the substrate so that the second recesses including the gate insulation layer are filled with the gate conductive layer; etching the gate conductive layer, so as to form gates including recess gates disposed in the second recesses and top gates disposed on the recess gates; forming spacers at both sides of the gates; and performing source/drain ion implant on the resultant of the substrate, so as to form source and drain regions at both sides of each gate on the surface of the substrate including the spacers, wherein the source and drain regions have an even doping profile due to the existence of insulation buffer patterns. [0022] Here, the first recesses are formed at a depth of 100.about.300 .ANG.. The insulation buffer patterns are formed of a nitride layer or a nitric oxide layer. The insulation buffer patterns are formed at a depth of 100.about.300 .ANG. in the surface of the substrate and at a width of 50.about.500 .ANG. on the inner surface of the second recesses. The second recesses are formed at a depth of 500.about.1000 .ANG.. Continue reading... Full patent description for Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Recess channel transistor for preventing deterioration of device characteristics due to misalignment of gate layers and method of forming the same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. 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