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  Real-time configurable maskingUSPTO Application #: 20080107976Title: Real-time configurable masking Abstract: Methods, systems, and media to define a portion of a circuit pattern with a source of real-time configurable imaging are disclosed. Embodiments include hardware and/or software for directing a beam through a mask onto a wafer surface to outline a circuit pattern having an undefined area, directing a second beam to the semiconductor wafer surface to define a circuit structure in the undefined area to complete the circuit pattern on the semiconductor wafer surface, and directing the second beam onto a source of real-time configurable imaging. Embodiments may also include a mask to include an undefined area incorporated into the circuit pattern to leave a critical structure of the circuit pattern undefined. Several embodiments include a photolithography system including an exposure tool, a mask, a source of real-time configurable imaging, and addressing circuitry. (end of abstract) Agent: Ibm Coporation (rtp) C/o Schubert Osterrieder & Nickelson Pllc - Austin, TX, US Inventors: WILLIAM BORNSTEIN, ANTHONY CAPPA SPIELBERG USPTO Applicaton #: 20080107976 - Class: 430005000 (USPTO) Related Patent Categories: Radiation Imagery Chemistry: Process, Composition, Or Product Thereof, Radiation Modifying Product Or Process Of Making, Radiation Mask The Patent Description & Claims data below is from USPTO Patent Application 20080107976. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF INVENTION [0001] The present invention is in the field of semiconductor fabrication. More particularly, the present invention relates to methods and arrangements to expose a semiconductor wafer surface to a circuit pattern based upon a combination of a lithographic mask and a real-time configurable imaging system such as a digital light processing system, a Kerr cell system, and a Pockel cell system. BACKGROUND [0002] Lithography is arguably the most critical and costly set of operations in fabricating integrated circuits. Lithography is a process used to transfer a pattern from a mask or reticle to a layer of resist deposited on the surface of a wafer. A mask or reticle may be a square glass or quartz plate with a patterned metal film such as chrome on one side. Further, different variations of lithography utilize different wavelengths of radiation to expose the photoresist. In particular, photolithography (or optical lithography) may use UV radiation, X-ray lithography may use X-rays, e-beam lithography may use an electron beam, and ion beam lithography may use an ion beam. The exposure transfers the pattern from the mask to the wafer's surface by physically altering the photoresist. [0003] Masks account for a large percentage of the cost of lithography. One semiconductor wafer may include many layers of circuitry, and a different mask may be used for each layer. For leading edge technologies, a mask set may cost $750,000. And, a large percentage of that money is spent controlling line widths. In particular, the industry drive toward smaller components has forced masks to include tiny, intricate details. In fact, the dimensions of the circuit patterns on the masks are so small that they are close to the wavelength of light used to expose the wafer's surface. Further, because the dimensions of the circuit patterns and the wavelength of the light, a straight line printed on (or outlined by) the mask may not necessarily expose the wafer's surface to the straight line. The wafer's surface may be exposed to a line that is curved and rounded at the corners, creating a pattern in the photoresist that is slightly off and potentially causing a short or other defect in the resulting semiconductor circuit. Thus, an increasing number of error corrective techniques including, e.g., optical interference effects and diffraction effects, have been formulated to avoid such problems. [0004] After such a large investment in capital, time, and effort to create masks, completed masks may still be discarded because a portion of the circuit pattern needs to be updated or changed after manufacturing the mask. To combat the costs of changing circuit patterns after a mask set is produced, various solutions have been employed to repair masks. However, the cost and cycle time associated with making repairs to a mask set are substantial and there are additional considerations to address with mask repair. For instance, a short in a circuit pattern created on a wafer may be discovered during testing of a first run in production of semiconductor circuits and, if the affected circuitry cannot be bypassed without impairing the functionality of the semiconductor circuit, the mask(s) may be removed from the production line for repair and the entire production line may be stopped until the mask(s) are repaired. [0005] One solution is focused-ion beam (FIB) repair, which involves focusing a tight beam of ions on the mask to mill material away from a surface or deposit material on the surface. For example, to connect two unconnected lines, an FIB can deposit a small amount of aluminum in a small stripe between the two lines on a wafer. Or, in another example, FIB may repair a mask by milling away a portion of chrome contamination off the surface of a mask. In yet another example, FIB may deposit a little bar of chrome on the mask. [0006] Repairing the mask prevents repetition of the defect in all the semiconductor circuits and saves the cost of making an entirely new mask. However, FIB mask repair is limited to minor changes to a mask and is a "one-time only" technique. FIB requires that the mask be removed from the lithography equipment, inserted into the FIB system, repaired, cleaned, and replaced back into the lithography equipment. As a result, repairs are very time-consuming and additional repairs may significantly deteriorate the integrity of the circuit pattern on the mask. [0007] Beyond the capital, time, and effort expended for reparations of masks that result from problems with a mask set, small differences between product lines of semiconductor circuits such as changes to a clock circuit to modify the frequency of operations in the semiconductor circuit may require the creation of additional mask sets. Some design decisions are preferably made at the time of manufacture of semiconductor circuits. For example, design decisions may include a decision about clock frequency for the circuit because design decisions for the clock frequency may be based upon the market to which the product will be sold and current market conditions. [0008] Therefore, there is a need for methods and arrangements capable of real-time changes in a circuit design of a mask. SUMMARY OF THE INVENTION [0009] The problems identified above are in large part addressed by methods and arrangements to define a portion of a semiconductor circuit pattern with a real-time configurable imaging system. One embodiment provides a photolithography mask to operate in conjunction with a digital micromirror device. The specially designed mask contemplates a circuit pattern including opaque and translucent areas to outline a layer of an integrated circuit; and an undefined area incorporated into the circuit pattern to leave a critical structure of the circuit pattern undefined, the critical structure being definable by the digital micromirror device by reflecting a supplemental exposure beam onto a semiconductor wafer surface to complete the circuit pattern. [0010] Another embodiment provides a method to create an image on a semiconductor wafer surface. The method generally includes directing an exposure beam through a photolithography mask onto the semiconductor wafer surface to outline a circuit pattern having an undefined area, positioning mirrors of a digital micromirror device to reflect a second exposure beam onto the semiconductor wafer surface to define a circuit structure in the undefined area to complete the circuit pattern on the semiconductor wafer surface, and directing the second exposure beam onto the digital micromirror device. [0011] An additional embodiment provides a photolithography method. The method generally includes projecting a first exposure beam to a wafer surface, defining an optical path associated with an exposure tool, filtering the first exposure beam with a mask to project an incomplete circuit pattern onto the wafer surface, projecting a second exposure beam toward a digital micromirror device; and adjusting an array of micromechanical mirrors of the digital micromirror device to reflect a pattern of the second exposure beam into the optical path at the wafer surface, the array of micromechanical mirrors being capable of real-time, individual adjustment to reflect the pattern. [0012] A further embodiment provides a photolithography system to facilitate definition of a portion of a semiconductor circuit pattern with real-time configurable imaging. The system contemplates an exposure tool to expose a wafer surface to a beam via a mask, wherein the mask filters the beam to project a circuit pattern, the circuit pattern comprising an undefined area designed for a circuit structure; a source of real-time configurable imaging to filter a second beam with a pattern defined by the circuit structure, to project the circuit structure onto a portion of the wafer surface that is associated with the undefined area; and addressing circuitry to configure the source of real-time configurable imaging with the pattern based upon the circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS [0013] Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which, like references may indicate similar elements: [0014] FIG. 1 depicts an embodiment of a system including a beam source, lithographic mask, light source, digital light processor, and semiconductor wafer surface to create an image on a semiconductor wafer surface; [0015] FIG. 2 depicts an embodiment of a system including a beam source, lithographic mask, light source, Kerr cell, and semiconductor wafer surface to create an image on a semiconductor wafer surface; [0016] FIG. 3 depicts an embodiment of a system to print an image on a semiconductor wafer surface in stages; [0017] FIGS. 4A-C depict embodiments of a specially designed lithographic mask for use in conjunction with a source of real-time configurable imaging; [0018] FIG. 5A-B depicts embodiments of lithographic imaging including light, a lithographic mask, photoresist layer, polysilicon layer, oxide layer, semiconductor wafer, and light from a source of real-time configurable imaging; and [0019] FIG. 6 depicts an example of a flowchart to project an image on a semiconductor wafer surface that combines a design from a lithographic mask and a design from a source of real-time configurable imaging. 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