FREE patent keyword monitoring and additional FREE benefits. http://images1.freshpatents.com/images/triangleright (1K) REGISTER now for FREE triangleleft (1K)
FreshPatents.com Logo    FreshPatents.com icons
Monitor Keywords Patent Organizer File a Provisional Patent Browse Inventors Browse Industry Browse Agents
  
Browse Inventors: A | B | C | D | E | F | G | H | I | J | K | L | M | N | O | P | Q | R | S | T | U | V | W | X | Y | Z

Ravi Nair patents

Recent bibliographic sampling of Ravi Nair patents listed/published in the public domain by the USPTO (USPTO Patent Application #,Title):



06/25/15 - 20150177811 - Power management for in-memory computer systems
According to one embodiment, a method for power management of a compute node including at least two power-consuming components is provided. A power capping control system compares power consumption level of the compute node to a power cap. Based on determining that the power consumption level is greater than the...
Inventors: Pradip Bose, Alper Buyuktosunoglu, Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Augusto J. Vega (International Business Machines Corporation)

01/29/15 - 20150032968 - Implementing selective cache injection
A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing...
Inventors: Philip Heidelberger, Hillery C. Hunter, James A. Kahle, Ravi Nair (International Business Machines Corporation)

09/18/14 - 20140281629 - Power management for a computer system
Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor...
Inventors: Pradip Bose, Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

09/18/14 - 20140281605 - Power management for a computer system
Embodiments include a method for managing power in a computer system including a main processor and an active memory device including powered units, the active memory device in communication with the main processor by a memory link, the powered units including a processing element. The method includes the main processor...
Inventors: Pradip Bose, Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

09/18/14 - 20140281403 - Chaining between exposed vector pipelines
Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at...
Inventors: Thomas W. Fox, Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

09/18/14 - 20140281386 - Chaining between exposed vector pipelines
Embodiments include a method for chaining data in an exposed-pipeline processing element. The method includes separating a multiple instruction word into a first sub-instruction and a second sub-instruction, receiving the first sub-instruction and the second sub-instruction in the exposed-pipeline processing element. The method also includes issuing the first sub-instruction at...
Inventors: Thomas W. Fox, Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

09/18/14 - 20140281100 - Local bypass for in memory computing
Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Martin Ohmacht, Krishnan Sugavanam (International Business Machines Corporation)

09/18/14 - 20140281084 - Local bypass for in memory computing
Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Martin Ohmacht, Krishnan Sugavanam (International Business Machines Corporation)

07/10/14 - 20140195744 - On-chip traffic prioritization in memory
According to one embodiment, a memory device is provided. The memory device includes a processing element coupled to a crossbar interconnect. The processing element is configured to send a memory access request, including a priority value, to the crossbar interconnect. The crossbar interconnect is configured to route the memory access...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

07/10/14 - 20140195743 - On-chip traffic prioritization in memory
According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

06/19/14 - 20140173224 - Sequential location accesses in an active memory device
Embodiments relate to sequential location accesses in an active memory device that includes memory and a processing element. An aspect includes a method for sequential location accesses that includes receiving from the memory a first group of data values associated with a queue entry at the processing element. A tag...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

05/29/14 - 20140149680 - Low latency data exchange
According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

05/29/14 - 20140149673 - Low latency data exchange
According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

05/29/14 - 20140149464 - Tree traversal in a memory device
Embodiments relate to tree traversal in a memory device. An aspect includes a method for tree traversal in a memory device. The method includes receiving a pointer to a tree structure within memory of the memory device. An evaluation condition is received to identify a desired node of the tree...
Inventors: James A. Kahle, Jaime H. Moreno, Ravi Nair (International Business Machines Corporation)

05/15/14 - 20140136895 - Exposed-pipeline processing element with rollback
An aspect includes providing rollback support in an exposed-pipeline processing element. A system includes the exposed-pipeline processing element with rollback support logic. The rollback support logic is configured to detect an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

05/15/14 - 20140136894 - Exposed-pipeline processing element with rollback
An aspect includes providing rollback support in an exposed-pipeline processing element. A method for providing rollback support in an exposed-pipeline processing element includes detecting, by rollback support logic, an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Daniel A. Prener (International Business Machines Corporation)

05/15/14 - 20140136858 - Power-constrained compiler code generation and scheduling of work in a heterogeneous processing system
An active memory system includes a computer and an active memory device including layers of memory forming a three-dimensional memory device and individual columns of chips forming vaults in communication with a processing element and logic. The processing element is configured to communicate to the chips and other processing elements....
Inventors: Hans M. Jacobson, Ravi Nair, John K.p. O'brien, Zehra N. Sura (International Business Machines Corporation)

05/15/14 - 20140136857 - Power-constrained compiler code generation and scheduling of work in a heterogeneous processing system
A heterogeneous processing system includes a compiler for performing power-constrained code generation and scheduling of work in the heterogeneous processing system. The compiler produces source code that is executable by a computer. The compiler performs a method. The method includes dividing a power budget for the heterogeneous processing system into...
Inventors: Hans M. Jacobson, Ravi Nair, John K.p. O'brien, Zehra N. Sura (International Business Machines Corporation)

05/15/14 - 20140136811 - Active memory device gather, scatter, and filter
Embodiments relate to loading and storing of data. An aspect includes a method for transferring data in an active memory device that includes memory and a processing element. An instruction is fetched and decoded for execution by the processing element. Based on determining that the instruction is a gather instruction,...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, James A. Kahle, Jaime H. Moreno, Ravi Nair (International Business Machines Corporation)

05/08/14 - 20140130051 - Main processor support of tasks performed in memory
According to one embodiment of the present invention, a computer system for executing a task includes a main processor, a processing element and memory. The computer system is configured to perform a method including receiving, at the processing element, the task from the main processor, performing, by the processing element,...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

05/08/14 - 20140130050 - Main processor support of tasks performed in memory
According to one embodiment of the present invention, a method for operating a computer system including a main processor, a processing element and memory is provided. The method includes receiving, at the processing element, a task from the main processor, performing, by the processing element, an instruction specified by the...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

05/08/14 - 20140129799 - Address generation in an active memory device
Embodiments relate to address generation in an active memory device that includes memory and a processing element. An aspect includes a method for address generation in the active memory device. The method includes reading a base address value and an offset address value from a register file group of the...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

04/24/14 - 20140115294 - Memory page management
According to one embodiment, a method for operating a memory device includes receiving a first request from a requestor, wherein the first request includes accessing data at a first memory location in a memory bank, opening a first page in the memory bank, wherein opening the first page includes loading...
Inventors: Bruce M. Fleischer, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

02/13/14 - 20140047214 - Vector register file
An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

02/13/14 - 20140047211 - Vector register file
An aspect includes accessing a vector register in a vector register file. The vector register file includes a plurality of vector registers and each vector register includes a plurality of elements. A read command is received at a read port of the vector register file. The read command specifies a...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

02/06/14 - 20140040603 - Vector processing in an active memory device
Embodiments relate to vector processing in an active memory device. An aspect includes a method for vector processing in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in parallel. An...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Daniel A. Prener (International Business Machines Corporation)

02/06/14 - 20140040601 - Predication in a vector processor
Embodiments relate to vector processor predication in an active memory device. An aspect includes a method for vector processor predication in an active memory device that includes memory and a processing element. The method includes decoding, in the processing element, an instruction including a plurality of sub-instructions to execute in...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

02/06/14 - 20140040599 - Packed load/store with gather/scatter
Embodiments relate to packed loading and storing of data. An aspect includes a system for packed loading and storing of distributed data. The system includes memory and a processing element configured to communicate with the memory. The processing element is configured to perform a method including fetching and decoding an...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Jaime H. Moreno, Ravi Nair, Daniel A. Prener (International Business Machines Corporation)

02/06/14 - 20140040598 - Vector processing in an active memory device
Embodiments relate to vector processing in an active memory device. An aspect includes a system for vector processing in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform a method...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Daniel A. Prener (International Business Machines Corporation)

02/06/14 - 20140040597 - Predication in a vector processor
Embodiments relate to vector processor predication in an active memory device. An aspect includes a system for vector processor predication in an active memory device. The system includes memory in the active memory device and a processing element in the active memory device. The processing element is configured to perform...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair (International Business Machines Corporation)

02/06/14 - 20140040596 - Packed load/store with gather/scatter
Embodiments relate to packed loading and storing of data. An aspect includes a method for packed loading and storing of data distributed in a system that includes memory and a processing element. The method includes fetching and decoding an instruction for execution by the processing element. The processing element gathers...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Jaime H. Moreno, Ravi Nair, Daniel A. Prener (International Business Machines Corporation)

02/06/14 - 20140040592 - Active buffered memory
According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction...
Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, James A. Kahle, Jaime H. Moreno, Ravi Nair (International Business Machines Corporation)

08/23/12 - 20120216197 - Virtualizing the execution of homogeneous parallel systems on heterogeneous multiprocessor platforms
An embodiment of the invention is a virtual machine monitor that is executable by computer processor. The virtual machine monitor runs a virtual processor. When the virtual processor encounters a faulting instruction the virtual processor is unmapped from the physical processor, and generates a list of other physical processors that...
Inventors: Ravi Nair (International Business Machines Corporation)

04/12/12 - 20120089820 - Hybrid mechanism for more efficient emulation and method therefor
In a host system, a method for using instruction scheduling to efficiently emulate the operation of a target computing syste includes preparing, on the host system, an instruction sequence to interpret an instruction written for execution on the target computing system. An instruction scheduling on the instruction sequence is performed,...
Inventors: Ravi Nair, John Kevin O'brien, Kathryn Mary O'brien, Peter Howland Oden, Daniel Arthur Prener (International Business Machines Corporation)

08/04/11 - 20110191095 - Method and system for efficient emulation of multiprocessor address translation on a multiprocessor
A method (and structure) of mapping a memory addressing of a multiprocessing system when it is emulated using a virtual memory addressing of another multiprocessing system includes accessing a local lookaside table (LLT) on a target processor with a target virtual memory address. Whether there is a “miss” in the...
Inventors: Erik Richter Altman, Ravi Nair, John Kevin O'brien, Kathryn Mary O'brien, Peter Howland Oden, Daniel Arthur Prener, Sumeda Wasudeo Sathaye (International Business Machines Corporation)

11/11/10 - 20100287355 - Dynamic translation in the presence of intermixed code and data
A system for translating software in a first format into a second format includes a memory containing the software in the first format and an emulator coupled to the memory configured to translate the software from the first format to the second format. The system also includes a host engine...
Inventors: Ravi Nair, Kevin A. Stoodley (International Business Machines Corporation)

06/18/09 - 20090157377 - Method and system for multiprocessor emulation on a multiprocessor host system
A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of...
Inventors: Erik Richter Altman, Ravi Nair, John Kevin O'brien, Kathryn Mary O'brien, Peter Howland Oden, Daniel Arthur Prener, Sumedh Wasudeo Sathaye (International Business Machines Corporation)

International Business Machines Corporation

Archived*
(*May have duplicates - we are upgrading our archive.)

20120216197 - Virtualizing the execution of homogeneous parallel systems on heterogeneous multiprocessor platforms


###

The bibliographic references displayed about Ravi Nair's patents are for a recent sample of Ravi Nair's publicly published patent applications. The inventor/author may have additional bibliographic citations listed at the USPTO.gov. FreshPatents.com is not associated or affiliated in any way with the author/inventor or the United States Patent/Trademark Office but is providing this non-comprehensive sample listing for educational and research purposes using public bibliographic data published and disseminated from the United States Patent/Trademark Office public datafeed. This information is also available for free on the USPTO.gov website. If Ravi Nair filed recent patent applications under another name, spelling or location then those applications could be listed on an alternate page. If no bibliographic references are listed here, it is possible there are no recent filings or there is a technical issue with the listing--in that case, we recommend doing a search on the USPTO.gov website.

###



Sign up for the FreshPatents.com FREE Keyword Monitor and check for keyword phrases (ie. "RFID" , "wireless", "web development", "fuel cells" etc.)...You will be notified when new patent applications and inventions are published that match your keywords. Also you can save for later research public patent/invention documents using our FREE Organizer. It takes only 30 seconds to sign up or login.

Advertise on FreshPatents.com - Rates & Info

###

FreshPatents.com Support - Terms & Conditions