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Ramp gate erase for dual bit flash memoryRamp gate erase for dual bit flash memory description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080037330, Ramp gate erase for dual bit flash memory. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF INVENTION [0001]The present invention relates generally to memory devices or systems, and in particular to methods of erasing flash memory utilizing a ramped voltage control gate. BACKGROUND OF THE INVENTION [0002]Various memory types and approaches exist to both program and erase data for computers, PDAs, digital cameras, telephone systems, flash drives, audio devices, video equipment, and the like. For example, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), programmable read only memory (PROM), electrically erasable programmable read only memory (EEPROM), flash memory, and the like, are all presently available to provide data storage capability. [0003]Each memory type has particular advantages and disadvantages associated with it. For example, DRAM and SRAM, both volatile memory, have the advantage of allowing individual bits of data to be erased, one at a time, but such data is lost when power is removed from the memory device. EEPROM, alternatively, can be erased but has reduced data storage density, lower speed, and higher cost than DRAM and SRAM. EPROM, in contrast to EEPROM, is less expensive and has greater packing density but is more difficult to erase. [0004]Flash memory (non-volatile) was developed in the late 1980's, originating from EPROM (read only memory) and has become popular as it combines the advantages of the high packing density and the low cost of EPROM with the erasing ease of EEPROM. Flash memory is, for example, programmable, erasable, stores data in an array of floating gate transistors or cells, is re-writable and can hold its memory contents when power is removed from the device (nonvolatile memory). The charge level determines whether or not a flash memory cell turns "on" or "off" when a read voltage level is applied to a control gate of the cell. Flash memory is utilized in many portable electronic products, such as cell phones, laptop computers, voice recorders, MP3 players, cameras, PDAs, and the like, as well as in many large electronic systems, such as, planes, cars, locomotives, industrial control systems, etc. Flash memory is characteristically erasable and programmable in sectors of memory referred to as multi-bit blocks. A whole block of memory cells can be erased in a single action, or in a flash, which may have been how the device got its name. Programming is a technique for changing memory cell data from a logical "1" (erased state) to a logical "0" (programmed state) in a flash memory cell array. There are two schemes of programming flash memory, single-byte (word programming) and buffer programming. Some devices support, for example, the single byte/word method, or the buffer programming method, or both. [0005]The erase, program, and read operations are commonly performed by application of appropriate voltages to certain terminals of the memory cell. In an erase or write operation the voltages are applied so as to cause a charge to be removed or stored on the floating gate within the memory cell, respectively. In a read operation, appropriate voltages are applied so as to cause a current to flow in the cell, wherein the determined amount of such current is indicative of the value of the data stored in the cell. The memory device includes appropriate circuitry to sense the resulting cell current in order to determine the data stored therein, which is then provided to data bus terminals of the device for access by other devices in a system in which the memory device is employed. [0006]A traditional stacked gate memory cell generally has a source, a drain, and a substrate channel formed there between, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (referred to as a tunnel oxide) formed on the surface of, for example, a P-well, silicon substrate. The stacked gate also includes a conductive, polysilicon floating gate overlying the tunnel oxide and an oxide dielectric isolation layer overlying the floating gate. The stacked gate structure is often a multilayer structure such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer and lastly, a polysilicon control gate overlies the isolation dielectric layer. [0007]In a NOR architecture configuration, the control gate is connected to a wordline associated with a row of memory cells which together with other rows of cells form sectors of such memory cells. In addition, the drain regions of various cells are connected together by conductive bitlines. The channels of the various cells conduct current between the source and the drain in accordance with an electric field developed in the channel by the stacked gate structure. Respective drain terminals of the transistors within a single column are connected to the same bitline. In addition, respective flash cells associated with a given bitline have stacked gate terminals coupled to a different wordline, while all the flash memory cells in the array generally have their source terminals coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bitline and wordline using the peripheral decoder and control circuitry for programming (writing), reading or erasing functions. [0008]By way of further detail, the single bit stacked gate flash memory cell is programmed by a suitable mechanism, such as channel hot electron injection (CHE). Programming with CHE injection involves applying a relatively high voltage to the control gate and connecting the source to ground and the drain to a predetermined potential above the source but typically below the control gate voltage. When a resulting electric field is high enough, electrons collect enough energy to be injected from the source onto the floating gate. As a result of the trapped electrons, the threshold voltage of the cell increases, the voltage required to switch a MOSFET from a blocking state to a conducting state is increased. This change in the threshold voltage (and thereby the channel conductance) of the cell created by the trapped electrons is what causes the cell to be programmed. [0009]In order to erase a typical single bit, stacked gate, flash memory cell, a relatively high voltage is applied to the source (e.g., +5 volts), and the control gate is held at a high negative potential (e.g., -10 volts), while the drain is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide between the floating gate and the source. The electrons that are trapped in the floating gate flow are forced into the source region by way of Fowler-Nordheim tunneling through the tunnel oxide. As the electrons are removed from the floating gate, the cell is erased or set to "1". [0010]For a read operation, a certain voltage bias is applied across the drain to source of the cell transistor. The drain of the cell is connected to a bitline, which may be connected to the drains of other cells in a byte or word group. A source read voltage is applied at the source and a drain read voltage (greater than the source read voltage) is applied at the drain. A read gate voltage is then applied to the control gate (e.g., by way of the wordline) of the memory cell transistor that is greater than the drain read voltage in order to cause a current to flow from the drain to source. The read operation gate voltage is typically applied at a level between a programmed threshold voltage (Vt) and an un-programmed threshold voltage. The resulting current is measured, by which a determination is made as to the data value stored in the cell. [0011]Another type of flash memory is dual bit memory, which allows multiple bits of data or information to be stored in a single memory cell. In this technology, a memory cell is essentially split into two dual or complementary bits, each of which is formulated for storing one of two independent pieces of data. Each dual bit memory cell, like a traditional single bit cell, has a gate with a source and a drain. However, unlike a traditional stacked gate cell in which the source is always connected to an electrical source and the drain is always connected to an electrical drain, respective dual bit memory cells can have the connections of the source and drain reversed during operation to permit the addressing of the two bits. [0012]In virtual ground type architecture, dual bit memory cells are mounted on a semiconductor substrate with conductive bitlines (columns) formed therein. A multilayer "storage layer", referred to as a "charge-trapping dielectric layer", is formed over the semiconductor substrate. The charge-trapping dielectric layer can generally be composed of three separate layers: a first insulating layer, a charge-trapping layer, and a second insulating layer. Wordlines (rows) are formed over the charge-trapping dielectric layer generally perpendicular to the bitlines. Programming circuitry controls two bits per cell by applying a signal to the wordline, which acts as a control gate, and changing bitline connections such that one bit is stored by the source and drain being connected in one arrangement and a complementary bit is stored by the source and drain being connected in another arrangement. [0013]As with many aspects of the semiconductor industry, there is a continuing desire to scale down device dimensions to achieve higher device packing densities on semiconductor wafers. Similarly, increased device speed and performance are also desired to allow more data to be stored on smaller memory devices, and quicker access to that data, etc. Accordingly, there are ongoing efforts to, among other things, increase the number of memory cells that can be packed on a semiconductor wafer (or die). [0014]One technique to pack more memory cells/transistors into a smaller area is to form the structures and component elements closer together. Forming bitlines closer together, for example, shortens the width of the transistor and the associated length of a channel defined there between and therefore allows more devices to be formed within the same area. This can, however, cause certain undesirable phenomena to become more prevalent. For example, isolating two bits or charges stored within a charge trapping layer becomes increasingly difficult as the channel length is decreased and the bits are brought closer together. In this manner, the charge on the bits can contaminate or disturb one another, causing operations performed on the bits to be more challenging and introducing a greater opportunity for error. This interdependency or affect that bits can have on one another is sometimes referred to as complementary bit disturb (CBD). Accordingly, it would be desirable to be able to operate on, and in particular, to program and erase complementary bits of data to and from a memory cell in a manner that mitigates the affects that the bits have on one another while improving the Vt distribution of the erased and programmed bit states. This can become even more vexing when memory cells are cycled as will be discussed infra. [0015]Also, while flash memory offers a variety of benefits to the end user as discussed supra, employing flash memory also gives rise to several additional problems. Flash memory typically has a long programming and erasing time. The programming of a memory cell can often take milliseconds to reach a required charge level on the floating gate on the transistor. In addition, flash memory is often negatively impacted by over-erasing in that an excessive charge is removed from the floating gate of the memory cell. Corrective programming often has to be employed to mitigate the damage caused by over-erasing. [0016]In view of the foregoing, a need exists for an improved method of increasing the speed of erasure, increasing the reliability of memory cell and sector erasure, decreasing the power consumed during erasing operation, and other factors to become apparent in this disclosure. SUMMARY OF THE INVENTION [0017]The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, its primary purpose is merely to present one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. [0018]The present invention, in one embodiment, is directed to a method that erases dual level flash memory bits by applying a ramp gate erase voltage to the memory cell in order to erase dual bits in the memory cells. The two data bits can contain three or more data levels or data states including a blank level or erased state and two or more programmed levels. [0019]The present invention, in another embodiment, pertains to a ramping voltage control gate method that is applicable to cells having one or more physical bits per cell, and two or more programmed states per physical bit. [0020]The present invention, in yet another embodiment, pertains to a method of providing a "ramp gate" technique for erasing to a low level, the un-programmed bits of adjacent bit-pairs of multi-level dual bit memory cells, which tend to have an interdependent effect on one another. The invention also pertains to multi-level dual bit (MLDB) memory cells comprising two (complementary) bits in a single physical memory cell, wherein each bit can be programmed to multiple levels. In accordance with the present invention, one exemplary implementation of an MLDB memory cell comprises two complementary bits in a single physical cell, wherein each bit utilizes four program levels (e.g., L1, L2, L3, and L4), the cell called a "quad-bit cell" (QBC). As discussed in connection with the complementary bit disturb, however, such complementary bit-pairs existing within close confines may have an affect on one another that tends to alter the effective Vt of the bits within the MLDB cells. [0021]The present invention, in a further embodiment, is directed to a method for employing a ramped voltage gate erasure technique in accordance with the invention. The technique is used for erasing dual bit flash memory sectors in an efficient manner requiring less erasure pulses to erase a group of cells than the current art. In addition, the ramped voltage gate erasure technique utilizes less power than current techniques. The inventors recognized that applying a lower voltage erasure pulse initially (lower than the current art) and subsequently ramping and/or increasing the absolute value of the voltage of the erasure pulse that a memory sector could be erased with fewer erasure pulses, as contrasted to the current art process of applying a higher initial and fixed voltage erasure pulse. Continue reading about Ramp gate erase for dual bit flash memory... Full patent description for Ramp gate erase for dual bit flash memory Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Ramp gate erase for dual bit flash memory patent application. Patent Applications in related categories: 20090285029 - High-speed verifiable semiconductor memory device - A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Ramp gate erase for dual bit flash memory or other areas of interest. ### Previous Patent Application: Nonvolatile semiconductor memory, method for reading the same, and microprocessor Next Patent Application: Non-volatile memory device and associated method of erasure Industry Class: Static information storage and retrieval ### FreshPatents.com Support Thank you for viewing the Ramp gate erase for dual bit flash memory patent info. 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