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  Providing a low phase noise reference clock signalThe Patent Description & Claims data below is from USPTO Patent Application 20070075793. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application claims the benefit under 35 U.S.C. .sctn. 119(e) to U.S. Provisional Application No. 60/722,472, filed on Sep. 30, 2005, which is hereby incorporated by reference in its entirety. BACKGROUND [0002] The invention generally relates to providing a low phase noise reference clock signal, such as a reference clock signal for a phase locked loop, for example. [0003] A modern communication system typically includes a tunable frequency synthesizer for purposes of generating mixing signals for the system. The frequency synthesizer typically includes a phase locked loop (PLL) and a reference clock generator that provides a reference clock signal to the PLL. The PLL generates the output signal for the synthesizer; and the frequency of the output signal typically is a multiple of the frequency of the reference clock signal. The frequency ratio typically is established by a programmable feedback divider of the PLL. [0004] Modern wideband communications systems have frequency synthesizers that can be tuned over a very wide range at multi-GHz frequencies. It may be desirable for the PLL to have a relatively large bandwidth for purposes of rejecting phase noise that is generated by the controlled oscillator of the PLL. However, a large loop bandwidth may cause the reference clock signal to significantly contribute to the phase noise (i.e., the clock jitter) in the output signal of the synthesizer. The large ratio between the output clock frequency (in the GHz range, for example) and the reference clock frequency (in a tens of MHz range, for example) typically results in a large feedback divider modulus for the PLL and thus, a large gain for the phase noise and the spurious tones that exist in the reference clock path. [0005] Thus, there exists a continuing need for a frequency synthesizer that has a reference clock signal path that introduces an insignificant amount of phase noise and spurious tones to the reference clock signal. SUMMARY [0006] In an embodiment of the invention, a reference clock generator includes an oscillator to generate a periodic signal, a shaping circuit and a filter. The shaping circuit shapes the periodic signal to generate a clock signal. The filter is located between the oscillator and the shaping circuit. [0007] In another embodiment of the invention, a shaping circuit includes a first inverter to receive a sinusoidal signal and a chain of serially coupled inverters. The chain has an input terminal to receive the sinusoidal signal and an output terminal. The sizes of the inverters progressively increase from the input terminal to the output terminal. [0008] In another embodiment of the invention, a frequency synthesizer includes a clock generator to generate a reference clock signal and a phase locked loop to lock onto the reference signal to generate an output signal. The clock generator includes an oscillator that has first transistors. Each of the first transistors have substantially a first gate oxide thickness. The phase locked loop includes a charge pump that has second transistors. Each of the second transistors has substantially a second gate oxide thickness that is substantially greater than the first gate oxide thickness. [0009] In yet another embodiment of the invention, a frequency synthesizer includes a clock generator to generate a reference clock signal and a phase locked loop to lock onto the reference clock signal to generate an output signal. The clock generator includes an oscillator that has first transistors, and each of the first transistors has substantially a first gate oxide thickness. The phase locked loop includes a phase detector that has second transistors. Each of the second transistors has substantially a second gate oxide thickness that is substantially smaller than the first gate oxide thickness. [0010] Advantages and other features of the invention will become apparent from the following drawing, description and claims. BRIEF DESCRIPTION OF THE DRAWING [0011] FIGS. 1, 2 and 3 are schematic diagrams of frequency synthesizers according to embodiments of the invention. [0012] FIG. 4 is a schematic diagram of a squaring buffer according to an embodiment of the invention. [0013] FIG. 5 is a more detailed schematic diagram of the squaring buffer according to an embodiment of the invention. [0014] FIG. 6 is a schematic diagram of an alternative closed-loop shunt regulator for use with the squaring buffer according to an embodiment of the invention. [0015] FIG. 7 is a schematic diagram of a wireless system according to an embodiment of the invention. DETAILED DESCRIPTION [0016] Referring to FIG. 1, an embodiment of a frequency synthesizer 10 in accordance with the invention includes a phase locked loop (PLL) 60 and a reference clock generator 20 that provides a reference clock signal to the PLL 60. The PLL 60, once locked onto the reference clock signal, provides an output signal that has a predetermined phase and frequency relationship to the reference clock signal. The PLL 60 has a relatively high bandwidth, which makes the PLL 60 potentially susceptible to phase noise and spurious tone contamination in the reference clock signal. However, as described below, the reference clock generator 20 has features that produce a reference clock signal that has relatively low phase noise and an insignificant level of spurious tone contamination. [0017] It is noted that although a single PLL 60 is depicted in FIG. 1, in other embodiments of the invention, the frequency synthesizer 10 may generate multiple output signals having different frequencies and thus, may include multiple PLLs that receive the reference clock signal from the reference clock generator 20. [0018] In accordance with some embodiments of the invention, the reference clock generator 20 includes a crystal reference oscillator 24 that generates a reference sinusoidal signal at its output terminal The sinusoidal signal, in turn, propagates through an isolation buffer 28 and a filter 32 before reaching a squaring buffer 36. The squaring buffer 36, in turn, reshapes the received sinusoidal signal to form the reference clock signal that is provided to the PLL 60. [0019] More specifically, the squaring buffer 36 performs a non-linear edge squaring operation that effectively corresponds to a phase sampling operation that is capable of upconverting and downconverting phase noise and spurs that are parasitically coupled to the main signal path that carries the main sinusoidal signal. Therefore, the squaring buffer 36 is capable of producing noise and spurs in a band near the carrier frequency of the signal that is produced by the PLL 60, which means the PLL 60 may be incapable of filtering out these tones and spurs. However, the filter 32 is used to filter out noise and spurs from the signal that is provided to the squaring buffer 32 for purposes of preventing the up and down conversion of the noise and spurs, in accordance with some embodiments of the invention. [0020] As a more specific example, in accordance with some embodiments of the invention, the filter 32 may be a relatively low order passive filter that may be formed, for example, from a resistor-capacitor (R-C) network. It is noted that in accordance with some embodiments of the invention, the reference clock generator 20 may include one or more additional higher order filters for purposes of increasing the effectiveness of the high frequency noise and spur rejection. Continue reading... Full patent description for Providing a low phase noise reference clock signal Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Providing a low phase noise reference clock signal patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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