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Programmable system on a chipProgrammable system on a chip description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070176631, Programmable system on a chip. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of co-pending U.S. patent application Ser. No. 10/843,701, filed May 10, 2004, which claims priority from U.S. Provisional Patent Application Ser. No. 60/491,788, filed Jul. 31, 2003, both of which are incorporated by reference herein in their entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to integrated circuits. More particularly, the present invention relates to a system-on-a-chip integrated circuit device including a programmable logic block, at least one user non-volatile memory block, and analog circuits on a single semiconductor integrated circuit chip, flip chip, face-to-face, or other multiple die configuration. [0004] 2. Background [0005] Field-programmable gate array (FPGA) integrated circuits are known in the art. An FPGA comprises any number of logic modules, an interconnect-routing architecture and programmable elements that may be programmed to selectively interconnect the logic modules to one another and to define the functions of the logic modules. To implement a particular circuit function, the circuit is mapped into the array and the appropriate programmable elements are programmed to implement the necessary wiring connections that form the user circuit. [0006] An FPGA includes an array of general-purpose logic circuits, called cells or logic blocks, whose functions are programmable. Programmable buses link the cells to one another. The cell types may be small multifunction circuits (or configurable functional blocks or groups) capable of realizing Boolean functions of multiple variables. The cell types are not restricted to gates. For example, configurable functional groups typically include memory cells and connection transistors that may be used to configure logic functions such as addition, subtraction, etc., inside of the FPGA. A cell may also contain a plurality of flip-flops. Two types of logic cells found in FPGA devices are those based on multiplexers and those based on programmable read only memory (PROM) table-lookup memories. Erasable FPGAs can be reprogrammed many times. This technology is especially convenient when developing and debugging a prototype design for a new product and for small-scale manufacture. [0007] An FPGA circuit can be programmed to implement virtually any set of digital functions. Input signals are processed by the programmed circuit to produce the desired set of outputs. Such inputs flow from the user's system, through input buffers and through the circuit, and finally back out the user's system via output buffers referred to as input/output ports (I/Os). Such buffers provide any or all of the following input/output (I/O) functions: voltage gain, current gain, level translation, delay, signal isolation or hysteresis. The input/output ports provide the access points for communication between chips. I/O ports vary in complexity depending on the FPGA. [0008] Recent advances in user-programmable interconnect technology have resulted in the development of FPGAs which may be customized by a user to perform a wide variety of combinatorial and sequential logic functions. Numerous architectures for such integrated circuits are known. Examples of such architectures are found disclosed in U.S. Pat. No. 4,870,302 to Freeman, U.S. Pat. No. 4,758,745 to El Gamal et al., and U.S. Pat. No. 5,132,571 to McCollum et al. The architecture employed in a particular FPGA integrated circuit will determine the richness and density of the possible interconnections that can be made among the various circuit elements disposed on the integrated circuit and thus profoundly affect its usefulness. [0009] Traditionally, FPGAs and other programmable logic devices (PLDs) have been limited to providing digital logic functions programmable by a user. Recently, however, FPGA manufacturers have experimented with adding application specific integrated circuit (ASIC) blocks onto their devices (See, e.g., U.S. Pat. No. 6,150,837). Such ASIC blocks have included analog circuits (see U.S. Pat. No. 5,821,776). In addition, ASIC manufacturers have embedded programmable logic blocks in their devices to add programmable functionality to otherwise hardwired devices (See, e.g., devices offered (or formerly offered) by Triscend Corporation, Adaptive Silicon Inc., and Chameleon Systems. SUMMARY OF THE INVENTION [0010] A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, at least one non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another. [0011] A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings, which set forth an illustrative embodiment in which the principles of the invention are utilized. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 is a block diagram of one illustrative embodiment of a system-on-a-chip according to one aspect of the present invention. [0013] FIG. 2 is a simplified diagram of a portion of an illustrative interconnect architecture that may be used to interconnect the inputs and outputs of the various circuit elements of the system-on-a-chip of FIG. 1 to form user circuit systems. [0014] FIG. 3 is a block diagram of another illustrative embodiment of a system-on-a-chip that includes a volatile memory block such as an SRAM block. [0015] FIG. 4 is a block diagram of another illustrative embodiment of a system-on-a-chip based on use of a highly successful flash FPGA architecture, for the programmable logic block. [0016] FIG. 5 is a block diagram of another illustrative embodiment of a system-on-a-chip based on use of a flash FPGA architecture for the programmable logic block. [0017] FIG. 6 is a schematic diagram of an illustrative glitchless clock multiplexer that is suitable for use in the SOC of the present invention. [0018] FIG. 7 is a block diagram of a portion of the SOC of FIG. 5 showing analog I/O function circuits grouped into sets according to one illustrative embodiment of the present invention. [0019] FIG. 8 is a diagram of a pre-scaler circuit that can scale external voltages by one of eight factors. [0020] FIG. 9 is a diagram of an illustrative configuration for the amplifier of FIG. 7. Continue reading about Programmable system on a chip... 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