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Programmable capacitors and methods of using the same

Programmable capacitors and methods of using the same description/claims

The present application is a continuation of and claims priority to U.S. patent application Ser. No. 11/353,516, filed Feb. 14, 2006, which is hereby incorporated by reference herein its entirety.

The present application is related to U.S. patent application Ser. No. 11/353,493, filed Feb. 14, 2006 and titled “MEMORY ELEMENTS AND METHODS OF USING THE SAME” (Attorney Docket No. ROC920050313), which is hereby incorporated by reference herein in its entirety.

The present invention relates generally to semiconductor devices, and more particularly to programmable capacitors and methods of using the same.

A conventional transistor may be employed as a capacitor. A plurality of such transistors may be coupled to form an array of capacitors. However, a large amount of circuitry and additional process complexity are required to maintain a state of the capacitor array. Further, such a conventional transistor may not provide low leakage (e.g., voltage or capacitance leakage), a wide tuning range and be adapted to integrate easily into existing complementary metal-oxide-semiconductor field effect transistor (CMOS) processing. Accordingly, an improved capacitor and circuitry formed thereby, and methods of using the same are desired.

In a first aspect of the invention, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the step of providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25. The transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage. The changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode. The first method also includes the step of employing the transistor in a circuit.

In a second aspect of the invention, a first apparatus is provided. The first apparatus is a semiconductor device having an adjustable capacitance that includes a transistor formed on a substrate having a gate region including a dielectric material having a dielectric constant of about 3.9 to about 25. The transistor is adapted to (1) operate in a first mode to provide a capacitance; and (2) operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode.

In a third aspect of the invention, a first system is adapted to provide a variable capacitance. The first system is a circuit that includes at least one transistor including a dielectric material having a dielectric constant of about 3.9 to about 25. Each transistor is adapted to operate in a first mode to provide a capacitance. Further, each transistor is adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode. A capacitance provided by the circuit is based on the capacitance provided by each transistor. Numerous other aspects are provided in accordance with these and other aspects of the invention.

Other features and aspects of the present invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

FIG. 1 is a graph illustrating a relationship between capacitance ratio and voltage.

FIG. 2 is a schematic diagram of a phase-locked loop (PLL) including a programmable capacitor in accordance with an embodiment of the present invention.

FIG. 3 is a schematic diagram of a first exemplary voltage-controlled oscillator (VCO) included in the PLL in accordance with an embodiment of the present invention.

FIG. 4 is a schematic diagram of a second exemplary VCO included in a modified version of the PLL in accordance with an embodiment of the present invention.

FIG. 5 is a schematic diagram of a capacitor array including at least one programmable capacitor in accordance with an embodiment of the present invention.

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