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  Processing activity masking in a data processing systemUSPTO Application #: 20060117167Title: Processing activity masking in a data processing system Abstract: Within a data processing systems supporting conditional write processing operations, a trash register is provided such that when non-write conditions are encountered a register write is made to the trash register rather than the data register specified by the conditional write operation. Thus the power signature associated with whether or not a register write does or does not occur is masked. The trash register activity may be programmable enabled and disabled by a configuration parameter stored within a system configuration register. (end of abstract) Agent: Nixon & Vanderhye, PC - Arlington, VA, US Inventors: Christophe Justin Evrard, Julie-Anne Francoise Marie Pruvost USPTO Applicaton #: 20060117167 - Class: 712208000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Instruction Decoding (e.g., By Microinstruction, Start Address Generator, Hardwired) The Patent Description & Claims data below is from USPTO Patent Application 20060117167. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This invention relates to the field of data processing systems. More particularly, this invention relates to the masking of processing activity within data processing systems, for example, in order to increase security. [0002] It is known to provide data processing systems which manipulate secure data and for which it is desirable to ensure a high degree of security. As an example, it is known to provide smart cards which include a data processing system which manipulates secure data, such as secret cryptographic keys, and this data must be kept secret in order to prevent fraud. [0003] Known ways of attacking the security of such systems include timing analysis and power analysis. By observing the tiling behaviour and/or the power consumption behaviour of such a system in response to inputs, information concerning the processing being performed and the data being manipulated can be determined in a way that can compromise security. It is strongly advantageous to provide resistance against such security attacks. [0004] Viewed from one aspect the present invention provides apparatus for processing data, said apparatus comprising: [0005] a result data value generating circuit operable to generate a result data value upon execution of a data processing operation; and [0006] a data processing register to which said result data value is written; wherein [0007] at least one data processing operation executed by said result data generating circuit is a conditional write data processing operation for which a result data value is not written to said data processing register when non-write conditions are met; and further comprising [0008] a trash register to which a result data value may be written upon execution of said conditional write data processing operation when said non-write conditions are met. [0009] This invention recognises that there is a characteristic power consumption signature associated with a write to a data processing register and accordingly information concerning the data processing being performed in association with conditional write data processing operations can be externally observed, i.e. information upon whether or not the conditional write did or did not occur. The invention address this problem by providing a trash register to which a result value (which is preferably the true value) is written when the conditional write data processing operation meets its non-write conditions and a write would not otherwise occur. Accordingly, a write to a register whether the true register or the trash register, always occurs irrespective of whether or not the write conditions or non-write conditions are met and thus the security of this system is enhanced. [0010] The data register to which the write is normally made when the write conditions are met is preferably part of a register bank containing a plurality of such registers. In this circumstance, a common trash register(s) may be used for dummy writes irrespective of how many real data registers are provided within the register bank. [0011] Preferably, the trash register is physically located as part of the register bank so as to avoid leakage of information by observing which part of a circuit is active at any given time. [0012] Whilst the present technique is applicable to a wide variety of systems, such a microprocessor based systems, digital signal processing system and the like, the invention is particularly well suited to systems including a processor core responsive to data processing instructions as these often incorporate conditional write instructions which give rise to the potential vulnerability addressed by this technique. [0013] It will be appreciated that a conditional write operation may be arranged to either occur or not occur when particular conditions are met. [0014] It will be appreciated that the normal technical prejudice in this field is to reduce power consumption as much as possible. Accordingly, it would conventionally be considered that not performing a register write when a conditional write operation did not require one would be an advantageous feature since it would reduce the amount of power consumed. The present technique moves against this technical prejudice in the field by deliberately performing a trash register write and consuming power even though this is not required for the real processing activities of the system. [0015] In preferred embodiments of the invention the trash register activity can be selectively enabled and disabled depending upon a control signal stored in a system configuration register. This allows programmable activity of the trash register activity such that power can be saved by disabling this feature when non secure processing is taking place and yet security improved when required, such as when handling cryptographic keys, decoding passwords etc. [0016] As mentioned above, whilst the trash register may be physically located within the register bank with the normal data registers, in preferred embodiments the trash register is unmapped to a register number such that it cannot be specified by any program instruction and accordingly is invisible as a register from the programmer's model point of view. The trash register is however visible in the sense that its activity can be enable or disabled in preferred embodiments by a configuration parameter. [0017] Viewed from another aspect the present invention provides a method of processing data, said method comprising the steps of: [0018] generating a result data value upon execution of a data processing operation, at least one data processing operation executed being a conditional write data processing operation, wherein [0019] a result data value is not written to a data processing register when non-write conditions are met but is instead written to a trash register. [0020] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings in which: [0021] FIG. 1 schematically illustrates a data processing system operable in a fixed timing mode and a variable timing mode; [0022] FIG. 2 schematically illustrates a conditional programming instruction; [0023] FIG. 3 is a flow diagram schematically illustrating part of the processing operations performed by an instruction decoder operating in accordance with the present techniques; [0024] FIG. 4 schematically illustrates the execution of a conditional branch instruction in a fixed timing mode; Continue reading... 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