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  Process for reducing dishing and erosion during chemical mechanical planarizationUSPTO Application #: 20080090500Title: Process for reducing dishing and erosion during chemical mechanical planarization Abstract: This invention is directed to a slurry system and process of metal removal from a substrate. This invention is useful for polishing a microelectronic device. This invention is especially useful for chemical mechanical planarization of a semiconductor wafer for removal of an overburden thereof. The slurry system of the present invention includes a first slurry and a second slurry, wherein the first slurry has a higher abrasive concentration than the second slurry. The process of the present invention includes a first polish with the first slurry to partially remove metal from the substrate, and a second polish with the second slurry to further remove metal from the substrate. (end of abstract) Agent: Deborah M. Altman Ppg Industries, Inc. - Pittsburgh, PA, US Inventors: Stuart D. Hellring, Yuzhuo Li, Robert L. Auger USPTO Applicaton #: 20080090500 - Class: 451057000 (USPTO) Related Patent Categories: Abrading, Abrading Process, Combined Abrading The Patent Description & Claims data below is from USPTO Patent Application 20080090500. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATIONS [0001] This application is a continuation in part of U.S. patent application Ser. No. 10/627,775 filed Jul. 28, 2003 which published Apr. 22, 2004 as publication number 2004/0077295 and which claims priority to U.S. patent application Ser. No. 60/401,109 filed Aug. 5, 2002, which publication is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention is directed to a process of metal removal from a substrate. This invention is useful for polishing a microelectronic device. This invention is especially useful for chemical mechanical planarization of a semiconductor wafer. [0004] 2. Background Information [0005] Microelectronic devices such as semiconductor wafers are typically fabricated with copper interconnects. These copper interconnects are produced by a multi-step damascene process which consists of etching trenches 12 into a dielectric material 14 such as silicon dioxide, inlaying a barrier film 16 such as tantalum into the trenches 12, and then filling the trenches 12 with electroplating copper 18. Generally, a thick copper overburden 20 is placed on top of the filled trenches. The application of this overburden 20 typically does not result in a flat surface. Instead, there are low areas in the overburden corresponding to the filled-in trenches underneath and high areas corresponding to the space in-between the trenches (i.e., "step-height topography"). This is generally shown in FIG. 1. [0006] In order to place another interconnect level on the microelectronic device, removal of the copper overburden layer 20 is required. Chemical mechanical planarization ("CMP") is a known technique for removing the copper overburden layer 20. During the CMP process, the copper overburden 20 is cleared from the surface of the microelectronic device to reveal the actual interconnect patterns. In a typical chemical mechanical polishing process, the microelectronic device is placed in contact with a polishing pad. The pad is rotated while a force is applied to the backside of the microelectronic device. An abrasive-containing chemically-reactive solution, commonly referred to as a "slurry", is applied to the pad during polishing. Typically, CMP polishing slurries contain an abrasive material, such as silica, alumina, ceria or mixtures thereof. The polishing process is facilitated by the rotational movement of the pad relative to the substrate as slurry is provided to the device/pad interface. Polishing is continued in this manner until the desired film thickness is removed. [0007] Depending on the choice of abrasive, and other additives, the polishing slurry may be formulated to provide effective polishing to metal layers at desired polishing rates while minimizing surface imperfections, defects, corrosion, and erosion. [0008] Processes for removal of copper overburden 20 using an abrasive slurry is known in the art. A disadvantage in these known processes include the tendency of the pressure of the polishing pad to press the abrasive particles into the surface of the substrate, resulting in dishing within the trenches and erosion of the pattern on the substrate. It is desirable in the art to minimize such dishing and erosion. Thus, there is a need in the art for a method of efficiently removing the copper overburden 20 while minimizing dishing within the trenches and erosion of the pattern on the substrate. SUMMARY OF THE INVENTION [0009] It is noted that, as used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless expressly and unequivocally limited to one referent. [0010] For the purposes of this specification, unless otherwise indicated, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about." Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and attached claims are approximations that may vary depending upon the desired properties sought to be obtained by the present invention. At the very least, and not as an attempt to limit the application of the doctrine of equivalents to the scope of the claims, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. [0011] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements. [0012] The features that characterize the present invention are pointed out with particularity in the claims which are part of this disclosure. These and other features of the invention, its operating advantages and the specific objects obtained by its use will be more fully understood from the following detailed description and the operating examples. [0013] It has been found that it is desirable to remove the step-height topography of the copper overburden in a first polishing step without clearing the entire overburden, such that a second step can be conducted to essentially clear the remaining overburden which is relatively free of step-height topography. A separate third step can be used to remove the barrier layer efficiently. [0014] According to one non-limiting aspect of the present invention, the present invention provides a slurry system for removal of a copper metal overburden from a substrate a microelectronic substrate comprising: (a) a first slurry which comprises abrasive and provides for partial removal of said copper metal from said microelectronic substrate, wherein the first slurry defines a first static etch rate of the copper metal overburden; and (b) a second slurry which provides for further removal of said copper metal from said microelectronic substrate, wherein said first slurry has higher concentration of said abrasive than said second slurry and wherein the second slurry has less than 70% of the static etch rate of the first slurry. [0015] According to one non-limiting aspect of the present invention, the present invention provides a third slurry configured for removal of the barrier layer following the removal of the overburden with the two slurry system. [0016] According to one non-limiting aspect of the present invention, the present invention provides a method for polishing a microelectronic substrate to remove a metal overburden of the microelectronic substrate comprising the steps of: (a) performing a first polish with a first slurry and polishing pad, wherein said first slurry comprises abrasive; and (b) terminating the first polishing step of (a) prior to removal of the entire metal overburden leaving residual metal overburden on the substrate; and (c) performing a second polish with a second slurry and polishing pad wherein said first slurry has higher concentration of said abrasive than said second slurry, and wherein the second polishing step is performed to substantially remove only the residual metal overburden of the substrate, wherein the step of substantially removing only the residual metal overburden of the substrate is defined by leaving a trace amount of the residual metal overburden that is less than 5% of the total metal overburden whereby steps a-c) remove more than 95% of the metal overburden. [0017] According to one non-limiting aspect of the present invention, the present invention provides a method for polishing a microelectronic substrate to remove a metal overburden of the microelectronic substrate comprises the steps of: (a) applying to a substrate a first slurry which comprises an abrasive for a first polishing of the metal overburden; (b) terminating the first polishing step of (a) prior to removal of the entire metal overburden leaving residual metal overburden on the substrate; and (c) applying to said substrate a second slurry, wherein said first slurry has higher concentration of said abrasive than said second slurry, said second slurry has a lower static etch rate than a static etch rate of the first slurry and wherein the second polishing step is performed to substantially remove only the residual metal overburden of the substrate, wherein the step of substantially removing only the residual metal overburden of the substrate is defined by leaving a trace amount of the residual metal overburden that is less than 5% of the total metal overburden whereby steps a-c) remove more than 95% of the metal overburden. [0018] According to one non-limiting aspect of the present invention, the present invention provides a method of removal of the barrier layer after the overburden has been removed wherein the method comprises the use of a third slurry configured for removal of the barrier layer following the removal of the overburden with the two slurry system. [0019] These and other advantages of the present invention will be clarified in the description of the preferred embodiments taken together with the attached figures in which like reference numeral represent like elements throughout. BRIEF DESCRIPTION OF THE FIGURES [0020] FIG. 1 is a schematic view of a portion of a microelectronic substrate with a trench, barrier layer, interconnect and overburden; Continue reading... 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