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  Printed circuit board including embedded chips and method of fabricating the sameUSPTO Application #: 20080106879Title: Printed circuit board including embedded chips and method of fabricating the same Abstract: A printed circuit board having embedded chips, composed of a central layer having an embedded chip, an insulating layer formed on one surface or both surfaces of the central layer and having a via hole filled with conductive ink, and a circuit layer formed on the insulating layer and having a via hole and a circuit pattern electrically connected to the chip of the central layer through the via hole of the insulating layer. In addition, a method of fabricating a printed circuit board including embedded chips is provided. (end of abstract) Agent: Darby & Darby P.c. - New York, NY, US Inventors: Chang Sup Ryu, Doo Hwan Lee, Jin Yong Ahn, Myung Sam Kang, Suk Hyeon Cho USPTO Applicaton #: 20080106879 - Class: 361783000 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080106879. Brief Patent Description - Full Patent Description - Patent Application Claims
INCORPORATION BY REFERENCE [0001] The present application claims priority under 35 U.S.C. .sctn.119 to Korean Patent Application No. 2004-116805 filed on Dec. 30, 2004. The content of the application is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates, generally, to a printed circuit board (PCB) including embedded chips, and a fabricating method thereof. More particularly, the present invention relates to a PCB including embedded chips, which comprises a central layer having an embedded chip, an insulating layer formed on one surface or both surfaces of the central layer and having a through hole filled with conductive ink, and a circuit layer formed on the insulating layer and having a via hole and a circuit pattern electrically connected to the chip of the central layer through the through hole of the insulating layer, and a method of fabricating such a PCB. The method of fabricating the PCB according to the present invention includes forming a circuit layer having a predetermined circuit pattern, vertically forming a via hole through a base substrate having a cured resin layer and a non-cured resin layer, filling the via hole with conductive ink, instead of a plating process, superimposing a passive component or an active component on the base substrate, and heating and compressing the circuit layers and the insulating layers on the base substrate at one time, to manufacture a multi-layered PCB. [0004] 2. Description of the Related Art [0005] With the great improvement of electronic industries, to correspond to electronic products requiring miniaturization and high functionality, electronic technologies have been developed to insert resistors, capacitors, ICs (integrated circuits), etc., into substrates. [0006] Although discrete chip resistors or discrete chip capacitors have long since been mounted on PCBs, PCBs including embedded chips, such as resistors or capacitors, have only recently been developed. [0007] In techniques of manufacturing PCBs including embedded chips, the chips, such as resistors or capacitors, are inserted into an outer layer or an inner layer of the substrate using novel materials and processes, to substitute for conventional chip resistors and chip capacitors. [0008] That is, the PCB including embedded chips means that the chips, for example, capacitors, are embedded in the inner layer of the substrate itself or outer layer thereof. Regardless of the size of the substrate itself, if the chip is incorporated into the PCB, this is called an `embedded chip`. Such a substrate is referred to as an `embedded chip PCB`. [0009] The major characteristic of the embedded chip PCB is that the chip is intrinsically provided in the PCB without the need to mount the chip on the substrate. [0010] In general, fabrication techniques of the embedded chip PCB are largely classified into three types. [0011] First, a method of manufacturing a polymer thick film type capacitor is provided, including applying a polymer capacitor paste, which is then heat cured, that is, dried. Specifically, this method includes applying a polymer capacitor paste onto an inner layer of a PCB, and drying the polymer capacitor paste, on which a copper paste is then printed and dried, to form electrodes, thereby obtaining an embedded capacitor. [0012] Second, a method of manufacturing an embedded discrete type capacitor is provided, including coating a PCB with a ceramic filled photosensitive resin, which has been patented by Motorola Co. Ltd., USA (U.S. Pat. No. 6,606,793). The above method includes applying the photosensitive resin containing ceramic powder on the substrate, laminating a copper foil layer on the resin layer to form upper electrodes and lower electrodes, forming a circuit pattern, and then etching the photosensitive resin, thereby obtaining a discrete capacitor. [0013] Third, a method of manufacturing an embedded capacitor is provided, including separately inserting a dielectric layer having capacitance properties into an inner layer of a PCB, so as to substitute for a decoupling capacitor mounted on a PCB, which has been patented by Zycon Corp. Ltd., USA (U.S. Pat. No. 5,079,069). In this method, the dielectric layer having power electrodes and ground electrodes is inserted into the inner layer of the PCB, thereby obtaining a power distributed decoupling capacitor. [0014] To fulfill various functions and superb performance of electronic products, higher speed electronic components are increasingly required. Also, with the aim of increasing the speed of the component, a package bonding manner is changed from typical bonding manners, such as lead frame, wire bonding, pin type bonding, etc., into a small ball type bonding manner or a flip-chip bonding manner. [0015] In the case of a high speed product that adopts a flip-chip bonding manner or in the case of a central processing unit (CPU) or a graphic chip set, a clock is operated at a speed of 2 GHz or more. [0016] Such a CPU or chip set requires a short signal rising time and a high current, and is designed to further decrease intervals between signal lines of an IC, flip chip package and a main board for operation at high speeds. [0017] However, as the speed of the component increases, voltage fluctuation of a power line occurs, resulting in the generation of a lot of high frequency noise, such as SSN (Simultaneous Switching Noise) or delta-I (.DELTA.I). [0018] The high frequency noise (e.g., SSN) causes system delay or a logic fault, thereby decreasing the performance and reliability of the system. [0019] Therefore, the SSN may be effectively reduced by lowering the inductance of the power line when the current and the switching speed required for the operation of devices are unchangeable. In addition, the decoupling capacitor is used to reduce the voltage fluctuation of the power line. [0020] The decoupling chip capacitor is mounted to the power line, whereby a current required for switching the circuit can be directly fed. Thus, the inductance of the power line is shielded, and hence, a voltage drop phenomenon is remarkably lowered and the SSN may be reduced, too. [0021] FIGS. 1a to 1f sequentially show a process of fabricating a PCB including embedded chips, according to a first conventional technique, which is disclosed in Japanese Patent Laid-open Publication No. 2004-7006. [0022] In FIG. 1a, an insulating layer 1 is processed to have a hollow portion 3 therethrough, and also, through holes 2 are formed through the insulating layer 1 and filled with conductive ink. Continue reading... Full patent description for Printed circuit board including embedded chips and method of fabricating the same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Printed circuit board including embedded chips and method of fabricating the same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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