Power efficiency in microprocessors

Title: Power efficiency in microprocessors

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20080178021, Power efficiency in microprocessors.

1. A method of reducing the power consumption of a microprocessor system which comprises a microprocessor and a memory connected by at least one bus, said memory containing a plurality of data values, each represented by a plurality of bits, for transmission to said microprocessor via said at least one bus, and at least some of said data values containing unused bits, the method comprising the steps of: reading an initial data value from memory; setting unused bits in the initial data value to a predetermined bit value; separately considering each remaining data value in sequence, assigning a bit value to each unused bit in the considered data value, the assigned bit value being equal to a bit value of a corresponding bit in an adjacent data value.

2. A method as claimed in claim 1, wherein the data values are instructions for execution by the microprocessor,

3. A method as claimed in claim 1, wherein said adjacent data value is a data value to be transmitted to the microprocessor via the at least one bus immediately before or after transmission of the considered data value.

4. A method as claimed in claim 1, wherein said adjacent data value is stored immediately before the considered data value in said memory.

5. A method as claimed in claim 1, wherein said adjacent data value is stored immediately after the considered data value in said memory.

6. A method of reducing the power consumption of a microprocessor system which comprises a microprocessor and a memory connected by at least one bus, said memory containing a plurality of instructions, each represented by a number of bits, for transmission in a sequence for execution to said microprocessor via said at least one bus, and at least some of said instructions containing unused bits, the method comprising the steps of: for an initial instruction, assigning unused bits to a predetermined bit value; for remaining instructions, taken in the sequence: if the instruction has more than one possible following instruction, assigning unused bits in the instruction to be equal to a bit value of a corresponding bit in a preceding instruction; if the instruction has more than one possible preceding instruction, assigning unused bits in the instruction to be equal to a bit value of a corresponding bit in a following instruction; and in other instructions, assigning unused bits in the instruction to be equal to a bit value of a corresponding bit in an adjacent instruction; and storing the instructions in the memory.

7. A method as claimed in claim 6, wherein, in the other instructions, the unused bits in the instruction are assigned to be equal to a bit value of a corresponding bit in a following instruction.

8. A method as claimed in claim 6, wherein, in the other instructions, the unused bits in the instruction are assigned to be equal to a bit value of a corresponding bit in a preceding instruction.

9. A method as claimed in claim 6, wherein assignment of unused bits in the instruction is based on a consideration of the probabilities of different paths to and from said instruction.

10. A method as claimed in claim 6, wherein in the case of an instruction having more than one possible preceding instruction and more than one possible following instruction, assignment of unused bits in the instruction is based on a consideration of bits in multiple preceding and following instructions.

11. A method as claimed in claim 6, wherein in the case of an instruction having more than one possible preceding instruction and more than one possible following instruction, assignment of unused bits in the instruction is based on relative probabilities of each path.

12. A method of reducing the power consumption of a microprocessor system which comprises a microprocessor and a memory connected by at least one bus, said memory containing a plurality of instructions, each represented by a number of bits, for fetching via said at least one bus in a sequence for execution by said microprocessor, and at least some of said instructions containing unused bits, said microprocessor being a pipelined microprocessor that fetches n extra instructions ahead in the sequence, the method comprising the steps of: for an initial instruction, assigning unused bits to a predetermined bit value; for remaining instructions, taken in the sequence: if an instruction has more than one possible following instruction, assigning unused bits in a subsequent instruction that is n instructions after the instruction, to be equal to a bit value of a corresponding bit in an instruction preceding the subsequent instruction; if the instruction has more than one possible preceding instruction, assigning unused bits in the instruction to be equal to a bit value of a corresponding bit in a following instruction; and in remaining instructions with unused bits, assigning unused bits in the instruction to be equal to a bit value of a corresponding bit in an adjacent instruction; and storing the instructions in the memory.

Brief Patent Description - Full Patent Description - Patent Claims

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Previous Patent Application:
Data structure for budgeting power for multiple devices
Next Patent Application:
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Industry Class:
Electrical computers and digital processing systems: support

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