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  Plating processUSPTO Application #: 20080035489Title: Plating process Abstract: Methods of plating electrical contacts on a photosensitive device are provided. Also provided are methods of plating electrical contacts on solar cells. (end of abstract) Agent: John J. Piskorski Rohm And Haas Electronic Materials LLC - Marlborough, MA, US Inventors: George R. Allardyce, Kevin Bass, Joachim Rasch USPTO Applicaton #: 20080035489 - Class: 205263 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080035489. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001]The present invention relates generally to the field of metal plating. More particularly, the present invention relates to the field of metal plating of photovoltaic devices. [0002]Photovoltaic devices, such as solar cells, often include a semiconductor wafer which forms a single large PN junction. Electromagnetic radiation such as sunlight incident upon that junction produces electrical carriers in the device and generates an electrical current, which must be collected and conveyed to an external circuit. The generated current is roughly proportional to the incident radiation. Metallic patterns which are in ohmic contact with the two sides of the PN junction collect the current. Such metallic patterns need to provide a low resistance path to minimize resistive losses of the generated current. The metallic pattern must be limited in its physical extent, especially on the front surface of the device, so as to minimize surface area that is blocks incident radiant energy, i.e. energy lost for current generation purposes. Typically, the front metallic pattern includes narrow strips of very highly conductive material. [0003]In fabricating a flat plate silicon solar cell, a satisfactory metal pattern can be achieved by applying a thin patterned layer of an ohmic contact and barrier layer material and by subsequent metallization. One metallization approach is screen-printed silver paste, which provides a thick conductor of low enough resistance for many applications. The silver paste itself, however, is not of low enough resistance to provide optimum solar cell performance. A more conductive material such as plated silver or copper is needed to minimize resistive losses which lower the solar cell efficiency. Silver has been deposited electrolytically onto a photovoltaic device, where current has been generated in the device itself through the use of radiant energy. In such electrolytic silver plating process, uniform deposition of the silver layer is achieved when a voltage is applied to one surface of the device while simultaneously illuminating the opposite surface of the device with radiant energy. [0004]Conventional silver electroplating baths used for such light assisted plating are cyanide-containing. However, the use of cyanide-containing plating baths raises numerous concerns, such as handling, waste treatment and environmental concerns. There is a desire in the industry for suitable plating baths for use in light assisted plating of photovoltaic devices where such plating baths are cyanide-free. U.S. Pat. No. 5,882,435 (Holdermann) discloses a process for the electroplating of solar cells made of crystalline silicon. This patent exemplifies the use of cyanide-containing silver plating baths. Although this patent does mention that cyanide-free silver plating baths may be used, it states that such cyanide-free silver baths have inadequate stability under the conditions of illumination. [0005]Accordingly, there remains a need in the industry for suitable cyanide-free metal plating baths, particularly silver plating baths, that can be used in an electroplating process with illumination by radiant energy, and where such plating baths have sufficient stability under the conditions of use. [0006]The present invention, which fills the above deficiencies, provides a method of plating an electrical contact on a light-sensitive device displaying a photovoltaic effect (a "photovoltaic device"), including providing a semiconductive wafer having at least two major surfaces, the wafer having a photovoltaic junction formed therein so that when one of the major surfaces of the wafer is exposed to light, negative charges collect at a first of the major surfaces and positive charges collect at a second of the major surfaces, contacting the wafer with a cyanide-free metal plating bath, applying a potential to the plating bath and exposing the wafer to light to deposit a layer of metal onto the first major surface, wherein the plating bath is an aqueous solution and includes metal ions, at least one water-soluble nitro-containing compound, at least one surfactant, at least one amido-compound, and at least one component chosen from a water-soluble amino acid, a water-soluble sulfonic acid, and mixtures thereof. [0007]In another embodiment, a coating of a metal on the second major surface is provided prior to contacting wafer with the cyanide-free metal plating bath. In this embodiment, migration of the metal from the coating on the second major surface into the plating bath and thence to the negatively charged first major surface occurs. [0008]The cyanide-free metal plating baths used in the present invention have sufficient stability under the conditions of illumination used in light assisted electroplating to provide metal deposits on photovoltaic devices that meet desired specifications. [0009]FIG. 1 illustrates a photovoltaic device of the invention. [0010]FIG. 2 is a schematic representation of providing a metal coating on a photovoltaic device according to the invention. [0011]As used throughout this specification, the term "plating" refers to the deposition of a metal layer, such as by electroplating or electroless plating, as the context indicates. "Deposition" and "plating" are used interchangeably throughout this specification. The indefinite articles "a" and "an" are intended to include both the singular and the plural. The following abbreviations have the following meanings unless the context clearly indicates otherwise: .degree. C.=degrees Celsius; g=grams; mL=milliliter; L=liter; A=amperes; dm=decimeter; .mu.m=micrometers; and nm=nanometers. All percentages and ratios are by weight unless otherwise indicated. All ranges are inclusive and combinable in any order except where it is clear that such numerical ranges are constrained to add up to 100%. [0012]A wide variety of photovoltaic devices may be used in the present invention, such as, for example, solar cells. Such photovoltaic devices are typically produced using a semiconductor substrate, such as a semiconductor wafer. In one embodiment, solar cells are composed of monocrystalline or polycrystalline or amorphous silicon wafers. In another embodiment, solar cells are composed of polycrystalline silicon wafers. While the description below is with regard to silicon wafers, it will be appreciated by those skilled in the art that other suitable semiconductor wafers, such as gallium-arsenide, silicon-germanium, and germanium, may suitably be used with the present invention. When silicon wafers are used, they typically have a p-type base doping. [0013]The wafers may be circular, square or rectangular in shape or may be any other suitable shape. Such wafers may have a wide variety of dimensions. For example, circular wafers may have a diameter of 150 nm, 200 nm, 300 nm, 400 nm, or greater. [0014]The rear side of a wafer is metallized. The entire rear side may be metal coated or a portion of the rear side may be metal coated, such as to form a grid. Such rear side metallization may be provided by a variety of techniques, and may be done prior to the metallization of the front side of the wafer or may be done simultaneously with the metallization of the front side of the wafer. In one embodiment, a metal coating is applied to the rear side in the form of an electrically conductive paste, such as a silver-containing paste, an aluminum-containing paste or a silver and aluminum-containing paste. Such conductive pastes typically include conductive particles embedded in a glass matrix and an organic binder. Conductive pastes may be applied to the wafer by a variety of techniques, such as screen printing. After the paste is applied, it is fired to remove the organic binder. When a conductive paste containing aluminum is used, the aluminum partially diffuses into the rear side of the wafer, or if used in a paste also containing silver, may alloy with the silver. Use of such aluminum-containing paste may improve the resistive contact and provide a "p+"-doped region. Heavily doped "p+"-type regions by previous application of aluminum or boron with subsequent interdiffusion may also be produced. In one embodiment, an aluminum-containing paste may be applied to the rear side and fired before the application of the rear side metal coating. The residue from the fired aluminum-containing paste may optionally be removed prior to the application of the rear side metal coating. In an alternate embodiment, a seed layer may be deposited on the rear side of the wafer and a metal coating may be deposited on the seed layer by electroless or electrolytic plating. Such metal deposition on the seed layer on the rear side of the wafer may be performed simultaneously with the metal deposition on the front side of the wafer using the present invention. [0015]The front side of the wafer may optionally be subjected to crystal-oriented texture etching in order to impart to the surface an improved light incidence geometry which reduces reflections. To produce the semiconductor junction, phosphorus diffusion or ion implantation takes place on the front side of the wafer to produce an n-doped region and providing the wafer with a PN junction. [0016]A dielectric layer may optionally be added to the front side of the wafer. Such dielectric layer may serve as both a passivation layer and an antireflection layer. Suitable dielectric layers include, without limitation, silicon oxide layers such as SiO.sub.x, silicon nitride layers such as Si.sub.3N.sub.4, a combination of silicon oxide and silicon nitride layers, and a combination of a silicon oxide layer and/or a silicon nitride layer with a titanium oxide layer such as TiO.sub.x. In the foregoing formulae, x is the number of oxygen atoms. Such dielectric layer may be deposited by a number of techniques, such as by various vapor deposition methods. [0017]The front side of a wafer typically contains a metallized pattern. For example, the front side of a wafer may be composed of current collecting lines and current busbars. Current collecting lines are typically transverse to the busbars and typically have a relatively fine-structure (i.e. dimensions) relative to current busbars. [0018]In one embodiment, the front side of the wafer may be metallized using a conductive paste, which may be the same as or different from any conductive paste used on the rear side of the wafer. Any conductive paste used to metallize the front side of a wafer typically does not contain aluminum. The firing of any conductive paste used on the rear side and front side of a wafer may be performed in one operation or in separate operations. The temperature used in the firing of the paste will depend on the particular paste used, the thickness of any dielectric (or antireflective) layer used, among other factors. The choice of such temperature is well within the ability of those skilled in the art. Also, it will be appreciated by those skilled in the art that the firing process may be performed in an oxygen-containing atmosphere, an inert atmosphere, a reducing atmosphere, or a combination of any of these. For example, the firing may be performed at a first temperature in an atmosphere containing little oxygen and then at a second temperature under an inert atmosphere or under a reducing atmosphere, where the second temperature is higher than the first temperature. [0019]Following the firing process, the wafer may optionally be contacted with a buffered acid solution, such as a buffered hydrofluoric acid solution, to remove any oxide produced during the firing procedure. Such contact may be by spraying the solution on the wafer or by dipping the wafer into such solution or by any other suitable means. [0020]In another embodiment, the front side of the wafer is coated with an optional antireflective layer, such as silicon nitride. A trench pattern is then defined on the front side. The trench pattern reaches through the antireflective (or dielectric) layer and into the semiconductor body of the wafer. The trenches may reach a depth of 1 to 25 .mu.m into the semiconductor body of the wafer. Deeper or shallower trench depths may be employed. A variety of processes may be used to form the trench pattern, such as, but not limited to, laser ablation, mechanical means, and lithographic processes, all of which are well known in the art. Such mechanical means include sawing and scratching. Typical photolithographic processes include disposing an imageable material on the surface of the wafer, patterning the imageable material to form trenches, transferring the trench pattern to the wafer, depositing a metal layer in the trench pattern and removing the imageable material. In one embodiment, the imageable material is removed before the step of depositing a metal layer in the trench pattern. In another embodiment, the imageable material is removed after the step of depositing a metal layer in the trench pattern. When the imageable material is present during the metal deposition step, such imageable material should avoid any dyes, such as contrast dyes, that absorb in the wavelength of radiation used during the metal deposition step. Imageable material present during the plating step should contain a dye that is transparent to the wavelength of radiation used during the plating step. [0021]When the imageable material is a liquid, such material may be disposed on the surface of the wafer by any suitable technique such as, but not limited to, by spin coating, doctor blading, curtain coating, and roller coating. When the imageable material is a dry film, such material may be disposed on the surface of the wafer by lamination. [0022]The imageable material is patterned by exposing the imageable material to actinic radiation through a mask. The choice of actinic radiation will depend upon the particular imageable material selected. Suitable wavelengths of actinic radiation include, but are not limited to, 500 nm to below 200 nm such as 430 nm, 405 mm, 365=nm, 248 nm, and 193 mm, as well as extreme ultraviolet ("EUV"), and e-beam. Lasers may also be used to pattern the imageable material. [0023]The pattern in the imageable material is next transferred to the wafer substrate. Pattern transfer may be performed using wet chemical etching techniques or by using dry etching techniques. Suitable dry etching techniques include, without limitation, plasma etching such as reactive ion etching. The trench pattern typically is composed of lines of relatively narrow cross-sectional dimension which are current collecting lines and lines of relatively thick cross-sectional dimension which are busbars. The busbars are transverse to the current collecting lines. [0024]The imageable material may be removed using any suitable polymer remover, such as those sold by Rohm and Haas Electronic Materials (Marlborough, Mass.). Such removers may be alkaline, acidic or essentially neutral. Continue reading... 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