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  Plasma reaction chamber and captive silicon electrode plate for processing semiconductor wafersUSPTO Application #: 20060108069Title: Plasma reaction chamber and captive silicon electrode plate for processing semiconductor wafers Abstract: A plasma processing system for etching a semiconductor wafer comprises: 1) a plasma chamber in which the semiconductor wafer may be mounted; 2) an upper ring capable of being mounted on an upper opening of the plasma chamber, wherein a central portion of the upper ring forms a hole; and 3) an electrode plate having a plurality of vias therethrough. The electrode plate is disposed in the hole in the upper ring, wherein the central portion of the upper ring further forms a shelf for supporting the electrode plate in the hole. (end of abstract) Agent: Docket Clerk - Dallas, TX, US Inventor: James T. Gernert USPTO Applicaton #: 20060108069 - Class: 156345340 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060108069. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD OF THE INVENTION [0001] The present invention generally relates to plasma processing systems and, more specifically, to a plasma reaction chamber with a captive silicon electrode for dry plasma etching of semiconductor wafers. BACKGROUND OF THE INVENTION [0002] Plasma processing techniques, such as dry plasma etching, reactive ion etching, and ion milling techniques, provide numerous advantages over traditional chemical etching of semiconductor wafers. For example, plasma etching has a vertical etch rate that is much greater than the horizontal etch rate. This provides good control over the resulting aspect ratio (i.e., the height to width ratio of the resulting notch) of the etched features. Thus, plasma etching forms very fine features with high aspect ratios in very thin films. [0003] During the plasma etching process, large amounts of energy are added to a gas at relatively low pressure, thereby ionizing the gas. This forms plasma above the masked surface of the substrate (i.e., the semiconductor wafer). An electrical field is established between an electrode at the top of the etching chamber and the semiconductor wafer at the bottom of the etching chamber. The electrical potential of the substrate is adjusted so that charged particles in the plasma are propelled towards the substrate and collide substantially perpendicularly upon the wafer surface. The energy of the impact removes materials in the unmasked regions of the wafer surface. Reactive ion etching improves this process by using gases that are chemically reactive with the material being etched. Reactive ion etching combines the kinetic etching effects of the plasma particles with the chemical etching effect of the gas. [0004] The effectiveness of the etching process is greatly affected by the components of the etching chamber. Uniform etching rates may be achieved across the surface of the wafer by evenly distributing the plasma over the wafer surface. U.S. Pat. Nos. 4,595,484, 4,792,378, 4,820,371, and 4,960,488 disclose showerhead electrodes for distributing gas through holes in the electrodes. These patents generally describe gas dispersion disks having an arrangement of apertures tailored to provide a uniform flow of gas vapor to a semiconductor wafer. [0005] However, the showerhead electrodes that are commonly used in the industry are prohibitively expensive. For example, LAM Research Corporation provides a one-piece showerhead assembly comprising an electrode and a retaining ring. The showerhead assembly is inserted into the top of the etching chamber and costs about $4500. This is a consumable item that greatly increases the cost of using a dry plasma etching system. [0006] Therefore, there is a need in the art for an improved dry plasma etching system that costs less to operate than conventional dry plasma etching systems. In particular, there is a need in the art for an improved dry plasma etching system that uses a less expensive showerhead electrode. SUMMARY OF THE INVENTION [0007] To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a plasma processing system for etching a semiconductor wafer. According to an advantageous embodiment of the present invention, the plasma processing system comprises: 1) a plasma chamber in which the semiconductor wafer may be mounted; 2) an upper ring capable of being mounted on an upper opening of the plasma chamber, wherein a central portion of the upper ring forms a hole; and 3) an electrode plate having a plurality of vias therethrough. The electrode plate is disposed in the hole in the upper ring, wherein the central portion of the upper ring further forms a shelf for supporting the electrode plate in the hole. [0008] According to one embodiment of the present invention, the shelf is formed below the hole on the side of the upper ring towards the interior of the plasma chamber. [0009] According to another embodiment of the present invention, the shelf encircles the hole and projects inward towards a center of the hole. [0010] According to still another embodiment of the present invention, the shelf has an upper surface capable of supporting a perimeter region of a lower surface of the electrode plate when the electrode plate is inserted into the hole. [0011] According to yet another embodiment of the present invention, the plasma processing system further comprises a retaining ring disposed on an upper surface of the upper ring, wherein the retaining ring encircles and overlaps the hole and holds the electrode plate in place in the hole. [0012] According to a further embodiment of the present invention, the retaining ring is made of aluminum. [0013] According to a still further embodiment of the present invention, the electrode plate is made of a semiconductor material. [0014] According to a yet further embodiment of the present invention, the plasma processing system further comprises an O-ring capable of forming a gas-tight seal between the retaining ring and the electrode plate. [0015] In one embodiment of the present invention, the O-ring is disposed in a groove formed in the retaining ring. [0016] In another embodiment of the present invention, the O-ring is disposed in a groove formed in the electrode plate. [0017] Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation; the term "or," is inclusive, meaning and/or; the phrases "associated with" and "associated therewith," as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. BRIEF DESCRIPTION OF THE DRAWINGS [0018] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: [0019] FIG. 1 illustrates a cross-sectional view of selected portions of a conventional dry plasma etching system according to an exemplary embodiment of the prior art; [0020] FIG. 2 illustrates a cross-sectional view of selected portions of an improved dry plasma etching system and an improved showerhead electrode assembly according to an exemplary embodiment of the present invention; Continue reading... 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