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Planarization with reduced dishingRelated Patent Categories: Etching A Substrate: Processes, Mechanically Shaping, Deforming, Or Abrading Of SubstratePlanarization with reduced dishing description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070163993, Planarization with reduced dishing. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD [0001] This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to planarization of integrated circuit layers. BACKGROUND [0002] Consumers continually pressure integrated circuit manufacturers to provide devices that are smaller and faster, so that more operations can be performed in a given amount of time, using fewer devices that occupy a reduced amount of space and generate less heat. For many years, the integrated circuit fabrication industry has been able to provide smaller and faster devices, which tend to double in capacity every eighteen months or so. [0003] However, as integrated circuits become smaller, the challenges of fabricating the devices tend to become greater. Fabrication processes and device configurations that didn't present any problems at a larger device size tend to resolve into new problems to be overcome as the device size is reduced. For example, in the past there was very little incentive to planarize the various layers from which integrated circuits are fabricated, and which are formed one on top of another. Because the devices themselves were relatively wide, the relatively thin layers that were formed did not present many challenges to overcome in regard to surface topography. [0004] However, as the devices have been reduced in size they have become relatively narrower. Although layer thickness has also generally decreased, the surface topography of an underlying layer tends to create greater problems for the proper formation of the overlying layer to be formed, unless the underlying layer is planarized in some way prior to the formation of the overlying layer. [0005] There are several different methods used for planarizing a layer on an integrated circuit. For example, chemical mechanical polishing can be used to physically and chemically erode the surface of the layer against a polishing pad in a slurry that contains both physically and chemically abrasive materials. Further, electropolishing can be used to thin an electrically conductive layer. Unfortunately, neither process tends to produce surface topographies that are as flat as desired. [0006] For example, although each of these two planarization processes tends to preferentially remove higher portions of a layer, they also attack to at least some degree the lower portions of the layer. Thus, even the though the higher portions of the layer are removed at a rate that is somewhat greater than that of the lower portions, and hence some planarization does occur, there also tends to be some amount of dishing in the lower portions of the layer, where a greater amount of material is removed than is desired. [0007] What is needed, therefore, is a method whereby the dishing of planarized layers is reduced. SUMMARY [0008] The above and other needs are met by a method of forming a planarized layer on a substrate, where the substrate is cleaned and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer. [0009] In this manner, material is selectively removed from the high portions of the layer, which brings them to a level that is more nearly that of the low portions of the layer. Thus, when the resistive mask is removed, the planarization process more effectively produces a truly planarized layer. [0010] In various preferred embodiments, the layer is a metal layer, and most preferably is a copper layer. The resistive mask is preferably photoresist. The step of etching is preferably at least one of electropolishing the layer, wet etching the layer, or dry etching the layer. Preferably, the step of planarizing the surface is at least one of chemical mechanical polishing the surface and electropolishing the surface. The layer is preferably formed by depositing a barrier layer of at least one of tantalum nitride, tantalum, titanium nitride, and magnesium, depositing a seed layer of copper, and then electroplating copper. The substrate is preferably sputter cleaned using at least one of argon, hydrogen, and a fluorinated hydrocarbon. [0011] According to another aspect of the invention there is described a method of forming a planarized layer on a substrate, where the substrate is cleaned and the layer is formed on the substrate having a surface with high portions and low portions. A resistive mask is formed over the high portions of the layer, but not over the low portions of the layer. The surface of the layer is treated to make it more resistive to planarization, where the low portions of the layer are exposed to the treatment, but the high portions of the layer underlying the resistive mask are not exposed to the treatment. The resistive mask is removed from the surface of the layer, and the surface of the layer planarized. The high portions of the layer are eroded at a first rate and the low portions of the layer are eroded at a second rate that is less than the first rate, due to the treatment received by the low portions of the layer, to provide a planarized layer. [0012] In various preferred embodiments, the step of treating the surface of the layer includes at least one of implanting and plasma treating the surface of the layer with at least one of carbon, nitrogen, tantalum, tantalum nitride, titanium, and titanium nitride. Most preferably the layer is a copper layer. The step of planarizing the surface preferably includes at least one of chemical mechanical polishing the surface and electropolishing the surface. [0013] According to yet another aspect of the invention there is described a method of forming a planarized layer on a substrate, where the substrate is cleaned and the layer is formed having a surface with high portions and low portions. A planar layer is formed over the layer, and the planar layer is planarized down to the high portions of the surface of the layer. The planar layer and the surface of the layer are both planarized using a process that planarizes both the planar layer and the layer at a substantially equal rate, until at least the planar layer is substantially completely removed, to provide a planarized layer. Preferably, the step of forming the planar layer includes depositing at least one of spin on glass and flow fill dielectric. The step of planarizing the planar layer preferably includes chemical mechanical polishing the planar layer. Preferably, the step of planarizing the planar layer and the surface of the layer includes at least one of chemical mechanical polishing and electropolishing. BRIEF DESCRIPTION OF THE DRAWINGS [0014] Further advantages of the invention are apparent by reference to the detailed description when considered in conjunction with the figures, which are not to scale so as to more clearly show the details, wherein like reference numbers indicate like elements throughout the several views, and wherein: [0015] FIG. 1 is a cross sectional depiction of an integrated circuit showing a layer to be planarized, having high portions and low portions, [0016] FIG. 2 is a cross sectional depiction of an integrated circuit showing a resistive layer overlying the low portions of the layer to be planarized, [0017] FIG. 3 is a cross sectional depiction of an integrated circuit showing high portions that have been removed to substantially the same level as the low portions, [0018] FIG. 4 is a cross sectional depiction of an integrated circuit showing a planarized layer, [0019] FIG. 5 is a cross sectional depiction of an integrated circuit showing a resistive layer overlying the high portions of the layer to be planarized, [0020] FIG. 6 is a cross sectional depiction of an integrated circuit showing a treatment process of the low portions of the layer to be planarized, Continue reading about Planarization with reduced dishing... Full patent description for Planarization with reduced dishing Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Planarization with reduced dishing patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Planarization with reduced dishing or other areas of interest. ### Previous Patent Application: Method and device for contacting semiconductor chips Next Patent Application: Charge-free layer by layer etching of dielectrics Industry Class: Etching a substrate: processes ### FreshPatents.com Support Thank you for viewing the Planarization with reduced dishing patent info. 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