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  Placement method for decoupling capacitorsUSPTO Application #: 20060015835Title: Placement method for decoupling capacitors Abstract: A method for placing decoupling capacitors in an integrated circuit during placement and routing stage. In the placement method, a floor plan of the integrated circuit is created, and includes the relative locations of a plurality of functional units. A power mesh comprising a plurality power lines is then overlaid on the floor plan, and the floor plan is divided into a plurality of windows. A plurality of semiconductor cells are placed into a portion of the windows. It is then determined whether a residual area comprising two adjacent windows without functional units and semiconductor cells disposed therein and at least three parallel power lines running theretrough exists. A MOS capacitor is then placed in the detected residual area, serving as a decoupling capacitor. (end of abstract) Agent: Thomas, Kayden, Horstemeyer & Risley, LLP - Atlanta, GA, US Inventors: Chien-Chia Huang, Yu-Wen Tsai USPTO Applicaton #: 20060015835 - Class: 716008000 (USPTO) Related Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Floorplanning The Patent Description & Claims data below is from USPTO Patent Application 20060015835. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a placement method, and more particularly, to a placement method for decoupling capacitors in a semiconductor circuit and a semiconductor structure using the same. [0003] 2. Description of the Related Art [0004] A current trend in semiconductor design, particularly for application specific integrated circuits (ASICs) and advanced/complex semiconductor integrated circuit devices, such as microprocessors, is to lower operating power, thus trend driving power supply and device threshold voltages to lower levels. Another trend emphasizing the need for decoupling is that voltage scaling has lagged behind area/capacitance scaling. As the supply voltage (VCC) and device threshold voltage (Vt) drop, the ratio of noise voltage to Vt and VCC increase, since noise levels do not scale down at the same rate as Vt and VCC. Consequently, sensitivity to noise in these types of semiconductor integrated circuit devices increase. In order to minimize noise effects, decoupling capacitors are often needed in VLSI circuits. [0005] Capacitance per unit area provided by conventional capacitance cells, however, is low due to capacitance cell layout style and layout rule. SUMMARY OF THE INVENTION [0006] Therefore an object of the present invention is to place decoupling capacitors in an integrated circuit to minimize noise effects. [0007] According to the above mentioned object, the present invention provides a method for placing decoupling capacitors to in integrated circuit during the placement and routing stage of fabrication process. [0008] In the placement method, a floor plan of the integrated circuit is created during the placement and routing stage. The floor plan comprises the relative locations of a plurality of functional units. A power mesh is then overlaid on the floor plan. The power mesh comprises a plurality of power lines and divides the floor plan into a plurality of windows. A plurality of semiconductor cells are placed into a portion of the windows. First it is determined whether a residual area comprising two adjacent windows without functional units and semiconductor cells disposed therein and at least three parallel power lines running theretrough exists. A MOS capacitor is then placed in the detected residual area, serving as a decoupling capacitor. The MOS capacitor has a gate connected to the middle of the three power lines in the detected residual area, and a drain and a source are respectively connected to the remaining two power lines. [0009] According to the above objects, the present invention also provides a semiconductor structure. In the semiconductor structure, a plurality of functional units are disposed in a substrate, and a power mesh is disposed on the substrate. The power mesh comprises a plurality of first power lines and a plurality of second power lines, wherein the first and second power lines are arranged alternately. A MOS capacitor is disposed in the substrate, and has a gate connected to one of the first power lines, and a drain and a source respectively connected to the second power line adjacent to the first power line connected to the gate. BRIEF DESCRIPTION OF THE DRAWINGS [0010] The present invention can be more fully understood by the subsequent detailed description and examples with reference made to the accompanying drawings, wherein: [0011] FIG. 1 is a flowchart of the placement method for decoupling capacitors in an integrated circuit according to the present invention; [0012] FIG. 2A shows a floor plan of an integrated circuit; [0013] FIG. 2B shows a power mesh structure according to the present invention; [0014] FIG. 2C shows the floor plan with the power mesh structure shown in FIG. 2B; [0015] FIG. 2D shows a semiconductor structure according to the present invention; and [0016] FIG. 3 shows a structure diagram of MOS capacitor according to the present invention. DETAILED DESCRIPTION OF THE INVENTION [0017] FIG. 1 is a flowchart of the placement method for decoupling capacitors in an integrated circuit according to the present invention. In step S10, a floor plan 10 of the integrated circuit is created during the placement and routing stage, as shown in FIG. 2A. The floor plan 10 shows the relative locations of a plurality of functional units FU1 and FU2. In this case, the functional units can be memory cells, microprocessors or the others. [0018] FIG. 2B shows a power mesh structure 15. The power mesh 15 comprises a plurality of power lines P1.about.P19. For example, the power lines P1.about.P9 are typically assigned to first metal layer (M1), and the power lines P10.about.P19 are usually assigned to second metal layer (M2) The power lines P1, P3, P5, P7, P9, P11, P13, P15, P17 and P19 can be coupled to supply voltage VCC, and power lines P2, P4, P6, P8, P10, P12, P14, P16 and P18 can be coupled to ground GND, and vice versa. Power lines P1, P3, P5, P7 and P9 of the first metal layer (M1) and power lines P11, P13, P15, P17 and P19 of the second metal layer (M2) are connected to each other through contacts (not shown). Power lines P2, P4, P6 and P8 of the first metal layer (M1) and power lines P10, P12, P14, P16 and P18 of the second metal layer (M2) are connected to each other through contacts (not shown). The power lines of supply voltage VCC and GND are arranged alternately. [0019] Next, in step S20, the power mesh 15 is overlaid on the floor plan 10, dividing the floor plan into a plurality of windows W, as shown in FIG. 2C. Then, a plurality of semiconductor cells SU are placed into the windows W. The semiconductor cells SU can be logic gates, active devices, passive devices or a combination thereof. For example, the active devices comprise switching devices, transistors and the like, and the passive devices comprise resistors, capacitors, inductors and the like, and the logic gates comprises OR gate, NOR gate, AND gate, NAND gate or a combination thereof. [0020] In step S30, it is determined whether a residual area comprising two adjacent windows in the power mesh without functional units disposed therein and at least three parallel power lines running theretrough exists. As shown in FIG. 2C, for example, the residual area RA1 comprises two adjacent windows W1 and W2 and three parallel power lines P2.about.P4, with no functional units and semiconductor cells arranged therein. The residual area Ra2 comprises four adjacent windows W3.about.W4 and three parallel power lines P6.about.P8, with no functional units semiconductor cells SU arranged therein. Consequently, the residual areas RA1 and RA2 can be detected. Continue reading... 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