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Pin grid array zero insertion force connectors configurable for supporting large pin countsPin grid array zero insertion force connectors configurable for supporting large pin counts description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080026627, Pin grid array zero insertion force connectors configurable for supporting large pin counts. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001]The present invention relates generally to area array microelectronic interconnections, and more particularly relates to pin grid array type area interconnections. BACKGROUND OF THE INVENTION [0002]Pin grid arrays (PGAs) are commonly used in the microelectronics industry, for example, for connecting a chip module to a printed circuit board or printed wiring board, utilizing pins in an area under the module that plug into a corresponding socket on the printed circuit board. Alternatively, the module may utilize a socket in an area under the module which is adapted for receiving corresponding pins mounted on the printed circuit board. PGAs are commonly, although not always, referred to as zero insertion force (ZIF) connectors. The term "ZIF connector" generally refers to a socket arrangement wherein when the socket is open, a chip may be placed in the socket without any pressure at all, and when the socket is then closed, the contacts of the socket grip the pins of the chip. Micro-PGA sockets typically refer to a PGA socket configured having a pin spacing, also referred to as pin pitch or simply pitch, between adjacent pins that is about 1.27 millimeters (mm) or less. [0003]Micro-PGAs are often preferred to other types of area array sockets, such as, for example, land grid arrays (LGAs), primarily because assembly and disassembly are much easier and do not require actuating hardware with posts that extend through the printed circuit board. PGA sockets are often soldered to the printed circuit board in a surface mounted fashion. The module typically has pins extending downward. In a ZIF arrangement, the module and socket on the PCB are typically brought together such that the pins are inserted all at once into corresponding contact holes in the PGA socket, and then the socket contacts are brought into electrical and physical contact with the pins using a mechanism that moves a top plane of the socket laterally, thereby engaging each pin to the respective electrical connection at that grid location. [0004]Most high input/output (I/O) count chip modules (e.g., greater than about 100 pins) currently use a 1.00 mm pitch to interconnect to the printed circuit board, either by soldering, as ball grid arrays (BGAs), or by socketing with LGAs. PGAs, in contrast, are most commonly used on smaller I/O modules and often at a 1.27 mm pitch. PGA suppliers are now attempting to fabricate PGA sockets that have a large I/O count at a 1.00 mm pitch, but are struggling to achieve a 50 mm.times.50 mm array size. Conventional interconnection methodologies appear to be approaching a natural limit based at least in part on characteristics of the injection molding process typically used to fabricate the plastic component parts. For example, injection molding parts with sufficient uniformity and flatness is difficult, in part because the large area of a 50 mm.times.50 mm array makes the transport of molten plastic from the injection ports to all mold areas difficult and in part from shrinkage and thermally induced stress across the array. This precludes making PGAs as a single molded piece for large substrates such as those currently serviced by LGAs with I/O pin counts greater than about 7000. [0005]Accordingly, there exists a need for an improved PGA-type microelectronic interconnection capable of providing substantially large I/O pin counts (e.g., greater than about 7000) that does not suffer from one or more of the problems exhibited by conventional PGA-type area interconnections. SUMMARY OF THE INVENTION [0006]The present invention, in illustrative embodiments thereof, meets the above-noted need by providing a PGA-type socket which overcomes certain characteristic limitations associated with conventional PGA interconnections. The illustrative PGA socket has a finer pitch compared to standard PGA sockets, thereby allowing the PGA socket to receive integrated circuits (ICs) having larger I/O pin counts than what would have otherwise been achievable using conventional means. To accomplish this, in accordance with illustrative embodiments of the invention, two or more sub-socket components having a finer pitch (e.g., less than about 1.27 mm) are beneficially combined to form a larger effective ZIF PGA socket adapted to provide an electrical interconnection with large I/O pin count ICs. Each of the sub-socket components is configured to mechanically engage at least one of the other sub-socket components so that electrical connection between individual pins of an IC received by the socket and corresponding contacts of the socket are made at substantially the same time. [0007]In accordance with one aspect of the invention, a PGA socket comprising a plurality of sub-socket components, which when used in combination forms a larger effective socket, includes multiple apertures configured to receive corresponding pins of an IC. The PGA socket further includes multiple contact members, each of the contact members corresponding to a respective one of the apertures. The contact members are configured to movably engage corresponding pins of the IC upon respective movement of the apertures so as to provide electrical and mechanical contact thereto. Each of the sub-socket components is configured to mechanically engage at least one of the other sub-socket components such that the contact members in each of the sub-socket components are capable of electrically connecting to corresponding pins of the IC substantially simultaneously. [0008]These and other features, advantages and objects of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0009]FIG. 1 is a perspective view showing the underside of an illustrative IC module with pins arranged in four quadrants across an area of the module. [0010]FIG. 2 is a perspective view illustrating an enlargement of the underside of the IC module shown in FIG. 1 depicting pins extending vertically from the underside of the IC module. [0011]FIG. 3 is an exploded view depicting an illustrative ZIF PGA socket which can be modified for use with the present invention. [0012]FIG. 4 is a perspective view depicting the illustrative PGA socket shown in FIG. 3 as assembled. [0013]FIG. 5 is a perspective view depicting an exemplary ZIF PGA socket, formed in accordance with an embodiment of the present invention. [0014]FIG. 6 is an exploded perspective view depicting the exemplary ZIF PGA socket of FIG. 5 shown at a more advanced stage of assembly, in accordance with an embodiment of the invention. [0015]FIG. 7 is a perspective view of the exemplary ZIF PGA socket of FIG. 5 fully assembled and soldered onto a printed wiring board, in accordance with an embodiment of the invention. [0016]FIG. 8 is a perspective view depicting the exemplary ZIF PGA socket of FIG. 5 fully engaged with an IC module inserted therein, in accordance with an embodiment of the invention. [0017]FIG. 9 is a top plan view depicting an exemplary ZIF PGA socket, formed in accordance with another embodiment of the present invention. [0018]FIG. 10 is an exploded perspective view depicting at least a portion of the exemplary PGA socket shown in FIG. 9, in accordance with an embodiment of the invention. [0019]FIG. 11 is an exploded perspective view illustrating an enlargement of a slot-key linkage of the exemplary PGA socket shown in FIG. 9, in accordance with an embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION Continue reading about Pin grid array zero insertion force connectors configurable for supporting large pin counts... Full patent description for Pin grid array zero insertion force connectors configurable for supporting large pin counts Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Pin grid array zero insertion force connectors configurable for supporting large pin counts patent application. Patent Applications in related categories: 20090291583 - Electrical connector having linear actuator - An electrical connector assembly is shown having a housing member with a mating assist which rotatably draws complementary connectors together. The mating assist is actuated by way of a linear actuator which rotates the mating assist member. ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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