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  Phase locked loop utilizing frequency foldingUSPTO Application #: 20080106310Title: Phase locked loop utilizing frequency folding Abstract: A phase locked loop (PLL), including a phase-frequency detector receiving two clock signals and outputting a phase detection signal corresponding to the phase difference between the two clock signals is provided. A controller receives the phase detection signal and generates a first control signal and a second control signal according to the phase detection signal, an oscillator receiving the first control signal and outputting a first output clock signal with a folded period corresponding to the first control signal and a loop divider receiving the second control signal and the first output clock signal dividing the frequency of the first output clock signal by an integer unfolding divisor corresponding to the second control signal and outputting a second output clock signal coupled to the phase-frequency detector. The PLL eliminates unlocked frequencies for all process imperfections, has decreased circuit area and provides a broad output bandwidth. (end of abstract) Agent: Thomas, Kayden, Horstemeyer & Risley, LLP - Atlanta, GA, US Inventors: Jyh-Ting Lai, Chun-Nan Ke USPTO Applicaton #: 20080106310 - Class: 327158 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080106310. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001]1. Field of the Invention [0002]The invention relates to a phase locked loop, and in particular to a phase locked loop utilizing frequency folding. [0003]2. Description of the Related Art [0004]FIG. 1 is a schematic diagram of a conventional digital phase locked loop (DPLL) 100. As shown, the conventional phase locked loop 100 comprises a phase-frequency detector (PFD) 110, a controller 120, a digitally controlled oscillator (DCO) 130 comprising a fine tune circuit (FTC) 132 and a coarse tune circuit (CTC) 134, and a loop divider 140. The PFD 1 10 receives and detects the phase and frequency difference between a reference clock signal S.sub.R and a feedback clock signal S.sub.F, and generates a phase detection clock signal S.sub.PD based on whether the feedback clock signal S.sub.F is leading or lagging the reference clock signal S.sub.R. The phase detection clock signal S.sub.PD comprises an up control signal Su and a down control signal S.sub.D respectively determining whether the DCO 130 needs to generate an output clock signal S.sub.O with a higher or lower frequency (i.e. lower or higher period). The PFD 110 then provides the phase detection clock signal S.sub.PD to the controller 120. [0005]The controller 120 generates a control word Cw comprising a first control word C.sub.W1 and a second control word C.sub.W2 according to the phase detection clock signal S.sub.PD and then provides the first and second control words C.sub.W1 and C.sub.W2 respectively to the FTC 132 and CTC 134 within the DCO 130 to control the period of the output clock signal S.sub.0 generated by the DCO 130. The first and second control words C.sub.W1 and C.sub.W2 respectively determine a high-resolution part and a low-resolution part of the period of the output clock signal S.sub.O Typically, the first and second control words C.sub.W1 and C.sub.W2 respectively are thermal code and one-hot code, as is described in relation to FIG. 3. [0006]FIG. 2 shows the period T of the output clock signal S.sub.O corresponding to the control word Cw, illustrating the relationship of the high and low resolution parts of the output clock signal S.sub.O respectively with the first and second control word C.sub.W1 and C.sub.W2 of the control word C.sub.W. As shown, the period range T.sub.WHOLE of the output clock signal S.sub.O is separated into a plurality of partially overlapped sub-period ranges T.sub.1, T.sub.2 and so on to T.sub.M respectively corresponding to the second control word C.sub.W2=C.sub.W2 (1), C.sub.W2(2) and so on to C.sub.W2 (M). Each of the sub-period ranges T.sub.1 to T.sub.M is further separated into a plurality of sub-period ranges T.sub.11-T.sub.N1, T.sub.12-T.sub.N2, and so on to T.sub.1M-T.sub.NM. The sub-period ranges T.sub.11, T.sub.12, and so on to T.sub.1M all correspond to the first control word C.sub.W1=C.sub.W1 (1). Similarly, the sub-period ranges T.sub.21, T.sub.22, and so on to T.sub.2M all correspond to the first control word C.sub.W1=C.sub.W1 (2). The other sub-period ranges can also be analogized. The sub-period ranges T.sub.1 to T.sub.M with larger intervals belong to the low resolution part of the output clock signal S.sub.O, and the sub-period ranges T.sub.11 to T.sub.N1, T.sub.12 to T.sub.N2, and so on to T.sub.1M to T.sub.NM with smaller intervals belonging to the high resolution part of the output clock signal S.sub.O. [0007]When the FTC 132 and CTC 134 respectively receive the first and second control word C.sub.W1 and C.sub.W2, they cooperate to generate the output clock signal S.sub.O with a period having high and low resolution parts respectively corresponding to the first and control words C.sub.W1 and C.sub.W2, and then provides the output clock signal S.sub.O to the loop divider 140. Note that in the figure, the output clock signal S.sub.O generated by the CTC 134 and a fine-tune output clock signal S.sub.FO generated by the FTC 132 have the same frequency but different phases, thus, the fine-tune output clock signal S.sub.FO can replace the output clock signal S.sub.O to serve as an output of the DCO 130 to be provided to the loop divider 140. [0008]The loop divider 140 divides the frequency of the output clock signal S.sub.O by a predetermined integer to generate the feedback clock signal S.sub.F. As is well-known to those skilled in the art, the loop divider 140 can be removed such that the output clock signal S.sub.O is connected directly to the phase-frequency detector 110 to serve as the feedback clock signal S.sub.F. [0009]FIG. 3 is a schematic diagram of the DCO 130 in FIG. 1. As shown, the FTC 132 comprises delay buffers 31_1 to 31_N, and the CTC 134 comprises first delay buffers 32_1 to 32_M and second delay buffers 33_1 to 33_M. The delay buffers 31_1 to 31_N of the FTC 132 are respectively turned on or off according to one bit of the first control word C.sub.W1 (an N-bit thermal code) to provide different driving power to the CTC 134. Similarly, the first delay buffers 32_1 to 32_M of the CTC 134 are respectively turned on or off according to one bit of the second control words C.sub.W2 (a M-bit one-hot code) to provide different delay paths to fine-tune output clock signal S.sub.FO from the FTC 132. As a result the FTC 132 and CTC 134 cooperate to generate the output clock signal S.sub.O with a period having high and low resolution parts respectively corresponding to the first and second control words C.sub.W1 and C.sub.W2. [0010]The conventional DPLL 100, however, has several disadvantages. First, the CTC 134 occupies a large area of a chip for providing a sufficiently long delay period and hence broad bandwidth of the output clock signal S.sub.O. Second, the controller 120 has high hardware complexity and requires a large chip area to generate the second control code C.sub.W2 in one-hot code form. Third, as shown in FIG. 4, the period T of the output clock signal S.sub.O corresponding to control word C.sub.W in an unwanted case results from fabrication process variation, where the two adjacent first sub-period ranges T.sub.2 and T.sub.3 are not overlapped, inducing a forbidden period range T.sub.F and hence jitter of the output clock signal S.sub.O. To prevent this, a complicated design procedure and lengthy simulation are required to ensure that all of the first sub-period ranges T.sub.1-T.sub.M are partially overlapped. BRIEF SUMMARY OF THE INVENTION [0011]The invention provides a PLL capable of eliminating unlocked frequency for all process imperfections, decreasing circuit area of the DCO and the controller, and enlarging the frequency range of the output clock signal. [0012]The invention provides a phase locked loop, comprising a phase-frequency detector, a controller, an oscillator and a loop divider. The phase-frequency detector receives and detects a phase difference between a reference clock signal and a feedback clock signal, and outputs a phase detection signal corresponding to the phase difference. The controller receives the phase detection signal and generates a first control signal and a second control signal according to the phase detection signal. The oscillator receives the first control signal and outputs a first output clock signal with a period corresponding to the first control signal. The loop divider receives the second control signal and the first output clock signal, divides the frequency of the first output clock signal by an integer unfolding divisor corresponding to the second control signal and outputs a second output clock signal coupled to the phase-frequency detector. BRIEF DESCRIPTION OF THE DRAWINGS [0013]The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: [0014]FIG. 1 is a schematic diagram of a conventional digital phase locked loop (DPLL); [0015]FIG. 2 shows the period of an output clock signal corresponding to a control word in FIG. 1; [0016]FIG. 3 is a schematic diagram of a DCO of FIG. 2; [0017]FIG. 4 shows the period of an output clock signal corresponding to a control word of FIG. 1 in an unwanted case; [0018]FIG. 5 is a block diagram of a phase locked loop in accordance with an embodiment of the invention; and [0019]FIG. 6 shows the period of a first output clock signal corresponding to a first control signal and the period of a second output clock signal corresponding to a second control signal in FIG. 5. DETAILED DESCRIPTION OF THE INVENTION [0020]FIG. 5 is a block diagram of a phase locked loop 500 in accordance with an embodiment of the invention. As shown, the phase locked loop 500 comprises a phase-frequency detector (PFD) 510, a controller 520, an oscillator 530, a first loop divider 540, and a second loop divider 550. The PFD 510 receives and detects a phase difference between a reference clock signal S.sub.R and a feedback clock signal S.sub.F and generates a phase detection clock signal S.sub.PD based on whether the feedback clock signal S.sub.F is leading or lagging the reference clock signal S.sub.R. The phase detection clock signal S.sub.PD comprises an up control signal S.sub.U and a down control signal S.sub.D respectively determining whether the oscillator 530 and the first loop divider 540 need to generate a second output clock signal S.sub.O2 with a higher or lower frequency (i.e. lower or higher period). The PFD 510 then provides the phase detection clock signal S.sub.PD to the controller 520. Continue reading... Full patent description for Phase locked loop utilizing frequency folding Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Phase locked loop utilizing frequency folding patent application. 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