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  Phase change memory element with a peripheral connection to a thin film electrode and method of manufacture thereofUSPTO Application #: 20070252127Title: Phase change memory element with a peripheral connection to a thin film electrode and method of manufacture thereof Abstract: A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of one of the first and second electrodes contacts the phase change element thereby reducing the contact area between the phase change element and one of the electrodes thereby increasing the current density through the phase change element and effectively inducing the phase change at a first programming power. (end of abstract) Agent: Graham S. Jones, Ii - Poughkeepsie, NY, US Inventors: John Christopher Arnold, Lawrence Alfred Clevenger, Timothy Joseph Dalton, Michael Christopher Gaidis, Louis L. Hsu, Carl John Radens, Keith Kwong Hon Wong, Chih-Chao Yang USPTO Applicaton #: 20070252127 - Class: 257002000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Bulk Effect Device, Bulk Effect Switching In Amorphous Material The Patent Description & Claims data below is from USPTO Patent Application 20070252127. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to memory devices, and more particularly a Phase Change Memory (PCM) cell structure and methods of making and using the same. BACKGROUND [0002] Recently nonvolatile chalcogenide Random Access Memory (RAM) devices, made of the germanium-antimony-tellurium (Ge.sub.2Sb.sub.2Te.sub.5) chalcogenide material, have been regarded as the most promising next-generation memory devices. The term "chalcogen" refers to the Group VI elements of the periodic table; and the term "chalcogenide" refers to alloys containing at least one of these elements, e.g. the alloy of germanium, antimony, and tellurium, etc. Chalcogenide materials have been used in PCM devices, especially in both rewritable Compact Disk (CD) and Digital Video Disk or Digital Versatile Disc (DVD) devices. This kind of memory when introduced into semiconductor chips has many advantages over others in areas, e.g. scalability, high sensing margin, low energy consumption, and cycling endurance. In a common design for chalcogenide memory cells, the data is stored in a flat chalcogenide layer that can be deposited near the end of the CMOS interconnect process making it ideal for embedded applications. [0003] A chalcogenide memory element can be programmed and reprogrammed into high/low resistance states. In short, when a chalcogenide memory element is in the amorphous phase (or so called RESET state) it has high resistance; when it is in the crystalline phase, it shows low resistance (or called SET state). The resistance ratio between two SET and RESET states can be greater than 1,000 times, which provides high sensing margins. [0004] FIG. 1 shows the current voltage (I-V) characteristics of the germanium-antimony-tellurium (Ge.sub.2Sb.sub.2Te.sub.5) chalcogenide material which is bistable. When the applied voltage V of the amorphous chalcogenide material exceeds the threshold voltage (Vt), threshold switching occurs and the material turns from an "OFF" state with low current level into a dynamic "ON" state with high current. In the ON state, the carrier concentration is high and the resistance is as low as that in the crystalline state. [0005] Adequate energy must be driven into the device to change state from the "RESET" state to the "SET" state in the dynamic ON state for a device in the RESET state. FIG. 2 shows that to ensure SET programming of a device the temperature must be above the crystallization temperature (Tx) and which must be held for a certain period of time (t2). [0006] On the other hand, FIG. 2 also shows that for a "reset program" or changing a cell from SET to RESET, enough energy must be driven into the Chalcogenide device and the local temperature must rise above the melting temperature (Tm). A shorter period of time should be spent above Tm to avoid heating the surrounding materials. It is critical that a rapid quenching interval (t1) is required after the local heating interval to return to the amorphous phase (RESET). [0007] Because the rate of Joule heating of the phase change material during the RESET and SET cycles is determined largely by current density, reducing the contact area between the phase change material and the adjacent electrode is sufficient to reduce the switched volume. For example, during the RESET cycle, it is not necessary to melt the entire volume of phase change material if the current density, and thus Joule heating rate, and thus material temperature, is high enough to melt the material near one of the electrodes. Once enough material has been amorphized to span the breadth of the current path through the cell, the overall resistance of the cell will be high. Similarly, during the SET cycle, the overall cell resistance will fall once a sufficiently broad path of crystalline material is formed. In both cases, adjacent material may be left in the opposite state without affecting the overall cell resistance significantly. [0008] To read a chalcogenide memory device, a "READ" voltage is applied on the device; thus permitting detection of the current difference resulting from the different device resistance. The read voltage must be lower than the threshold voltage (e.g. 1.2V) to avoid changing the state of the material. [0009] Currently, chalcogenide devices are used in reversible (RW) optical information storage devices, e.g. CD-RW and DVD-RW disks. Compounds, e.g. a germanium-antimony-tellurium material (Ge.sub.2Sb.sub.2Te.sub.5), can change phase from amorphous to crystalline in about 50 ns after proper exposure to radiation from a laser beam. However, the crystallization speed of a germanium-antimony-tellurium material tends to decrease with thinner films. To avoid this, it is suggested that tin be doped into a Ge--Sb--Te compound to form a Ge--Sb--Sn--Te compound and increase the crystallization speed. TABLE-US-00001 TABLE I Possible Phase Change Materials Binary Ternary Quaternary GaSb Ge.sub.2Sb.sub.2Te.sub.5 AgInSbTe InSb InSbTe (GeSn)SbTe InSe GeSeTe GeSb(SeTe) Sb.sub.2Te.sub.3 SnSb.sub.2Te.sub.4 Te.sub.81Ge.sub.15Sb.sub.2S.sub.2 GeTe InSbGe [0010] A simplified cell structure of chalcogenide PCM type of memory comprises a conventional MOS FET transfer transistor connected to a memory cell. One source/Drain (S/D) junction of the transistor is connected to a metal wire called a bit-line. The other S/D junction of the MOS FET is connected to the memory element. The gate electrode of the transistor is connected to another metal line called the word-line. The PCM element comprises a sandwich of top electrode, a bistable dielectric, and a bottom electrode. Both electrodes are made of metal or refractory metal, while the bistable dielectric is a thin layer of a chalcogenide material. [0011] As to the cycling endurance of a chalcogenide memory element, it has been reported by Lai et al. that one can conduct more than 1E12 set/reset cycles, which is much higher than a conventional Flash memory (about 1E5). The report was made by Stefan Lai et al. in "Current Status of the Phase Change Memory and its Future" Electron Devices Meeting, 2003. IEDM 2003 Technical Digest. IEEE International 8-10 Dec. 2003, Pages: 10.1.1-10.1.4 [0012] Application of this class of PCM to a practical multi-bit memory device requires two additional characteristics beyond those discussed above as follows: [0013] (1) the volume of switched material (i.e., the material which changes phase) must be small, so that the currents required during the Set cycles and the Reset cycles are not excessive, and [0014] (2) the many memory cells in the multi-bit device must be sufficiently similar to each other than that good separation between the Set and Reset currents is maintained. [0015] If the switched volume is too large relative to the technology node at which the transistors are fabricated, the power required to switch that material (particularly during the Reset cycle) will be higher than the transistors connected to the PCM device can support reliably. Simulations and other studies have suggested that appropriate dimensions for the switched material will be on the order of one half (1/2) or one quarter (1/4) of the nominal technology node. Thus, for the 90 nm node, the memory cell will need to have characteristic dimensions in the 30-50 nm range. This is well below the lithographic capabilities defined for that technology node; and because the capacity for power delivery scales down with the technology node, it will be required that the PCM device will be sub-lithographic at all nodes. [0016] Furthermore, accurate control of the memory cell dimensions is essential. If the dimensions vary excessively, on an all-cells/all-die/all-days basis, there is a risk that the current applied during the Reset pulse may actually set the material in some cells, and vice-versa. [0017] Thus, the principal challenge in fabricating practical memory devices is in producing and controlling dimensions well below the norms for standard photolithography. [0018] This invention is one of several approaches designed to reduce the effective dimensions of the memory cell through additional processing after lithography. Other approaches include "trimming" photoresist blocks prior to transferring their dimensions into phase change materials, depositing phase change material in holes or trenches whose sidewalls have been intentionally tapered to provide a smaller contact area at the bottom of the hole than was defined by lithography at the top, and depositing dielectric liners inside conventionally-defined holes to reduce their dimensions prior to filling them with phase change material. [0019] Several prior art PCM cell designs have been reported. In the Lai et al. paper described above, "Current Status of the Phase Change Memory and its Future," FIGS. 7A/7B therein show configurations in which use is made of edge contact to reduce switching current. The PCM device includes a top electrode contact TEC, a top electrode TE, a chalcogenide PCM (GeSbT) layer GST, a bottom electrode BE, and a bottom electrode contact BEC. The programming current is significantly reduced by using an edge instead of conventional top and bottom electrode contact. The programmable volume in diagram 7B is much smaller than that of the conventional design. [0020] Another prior art approach is embodied in U.S. Pat. No. 6,764,894 B2, of Lowrey entitled "Elevated Pore Phase-Change Memory." As shown in FIG. 6 of Lowrey there is Shallow trench isolation (STI) 14, a base contact 16, a conductor 18, a fill insulator 20, cup-shape lower electrode 22, sidewall spacers 24 composed of an insulator, phase change material 28 (e.g. Ge.sub.2Sb.sub.2Te.sub.5), and an upper electrode 30. The Lowrey patent states "In some embodiments, a thermally efficient device structure provides for improved device performance by reducing the required power for device programming. The programmable media volume, represented by the phase-change layer 28, is nearly surrounded by thermal insulation." [0021] U.S. Pat. No. 6,800,563 of Xu entitled "Forming Tapered Lower Electrode Phase-Change Memories" shows in FIG. 7 thereof a conical substrate, a lower electrode, an upper electrode, and phase change material. In Xu a tapered lower electrode stack is created by isotropic etching. That design provides a relatively small surface area contacting with the phase change material. When current is flowing through the electrodes, the current density at the tapered contact is very high leading to a rapid rise of temperature there. The Xu patent indicates that the tapered shape of the lower electrode reduces the contact area between the electrode and the phase-change material. This increases the resistance at the point of contact, increasing the ability of the lower electrode to heat the PCM layer. [0022] U.S. Pat. No. 6,649,928, of Dennison entitled "Method to Selectively Remove One Side of a Conductive Bottom Electrode of a Phase-Change Memory Cell and Structure Obtained Thereby," relates to a PCM device including a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase change material. The second side has a length that is less than the first side. A second dielectric, which may overlie the lower electrode, has a shape that is substantially similar to the lower electrode. The method of the Dennison invention includes providing a lower electrode material in a recess and removing at least a portion of the second side. [0023] U.S. Pat. No. 6,791,102 of Johnson entitled "Phase Change Memory" describes a PCM device with phase change material having a bottom portion, a lateral portion, and a top portion. The PCM device may include a first electrode material contacting the bottom portion and the lateral portion of the phase change material and a second electrode material contacting the top portion of the phase change material. A first conductive material is cup-shaped and surrounds the bottom portion and the lateral portion of the phase change material. A lower electrode which is cup shaped, circular, or ring-shaped may be formed surrounding and contacting the lateral and bottom surfaces of the PCM memory material. [0024] U.S. Pat. No. 6,815,704 of Chen entitled "Phase Change Memory Device Employing Thermally Insulating Voids" describes a PCM device, and method of making the same, that includes contact holes formed in insulation material that extend down to and expose source regions for adjacent FET transistors. Lower electrodes are disposed in the holes with surfaces defining openings narrowed along a depth of the opening by spacers. A layer of phase change material is disposed along the spacer material surfaces and along the lower electrodes. Upper electrodes are formed in the openings and on the phase change material layer. Voids are formed in the spacer material to impede heat from the phase change material from conducting through the insulation material. For each contact hole, the upper electrode and phase change material layer form an electrical current path that narrows as the current path approaches the lower electrode. The electrical current pulse flowing through the upper electrode generates heat, concentrated in the lower portion thereof, where current density is greatest. The narrow current path of the upper electrode produces a maximum current density and maximum heat generation, adjacent to the memory material to be programmed, minimizing the amplitude and duration of electrical programming for the PCM device. The spacers surrounding the heating electrode increase the distance and thermal isolation between heating electrodes and programming material layers from adjacent cells. An indentation sharpens the tip of the upper electrode lower portion, focusing heat generation at the chalcogenide material disposed directly between the tip and the lower electrode. In one embodiment, voids isolate the memory cells thermally. Continue reading... Full patent description for Phase change memory element with a peripheral connection to a thin film electrode and method of manufacture thereof Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Phase change memory element with a peripheral connection to a thin film electrode and method of manufacture thereof patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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