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  Phase change material and non-volatile memory device using the sameUSPTO Application #: 20070120104Title: Phase change material and non-volatile memory device using the same Abstract: The present invention provides a phase change memory cell comprising (GeASbBTeC)1−x(RaSbTeC)x solid solution, the solid solution being formed from a Ge—Sb—Te based alloy and a ternary metal alloy R—S—Te sharing same crystal structure as the Ge—Sb—Te based alloy. A nonvolatile phase change memory cell in accordance with the present invention provides many advantages such as high speed, high data retention, and multi-bit operation. (end of abstract) Agent: David A. Einhorn, Esq. Anderson Kill Olick, P.C. - New York, NY, US Inventors: Dong Ho Ahn, Tae-Yon Lee, Ki Bum Kim, Byung-ki Cheong, Dae-Hwan Kang, Jeung-hyun Jeong, In Ho Kim, Taek Sung Lee, Won Mok Kim USPTO Applicaton #: 20070120104 - Class: 257002000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Bulk Effect Device, Bulk Effect Switching In Amorphous Material The Patent Description & Claims data below is from USPTO Patent Application 20070120104. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to a non-volatile memory device using a phase change material. BACKGROUND OF THE INVENTION [0002] In recent years, there has been a renewal of interest in phase change random access memory (PCRAM) as a promising candidate for next generation nonvolatile memory device because of many advantages such as non-volatility, fast operation property, process simplicity and possibility of multi-bit operation. [0003] Traditionally, PCRAM employs a chalcogenide-based phase change material such as a stoichiometric Ge--Sb--Te alloy like Ge.sub.2Sb.sub.2Te.sub.5. A Ge--Sb--Te based alloy is capable of storing information in a binary form by electrically switching between the amorphous and crystalline states in a reversible manner. [0004] Despite its merits as nonvolatile phase change memory material, however, a Ge--Sb--Te based alloy is disadvantageous as it tends to yield slow writing speed. For instance, it takes about 100 ns for the completion of the phase change from the amorphous (high resistance) to the crystalline (low resistance) states when a Ge--Sb--Te based alloy is employed. It takes ordinarily less than 100 ns in the reverse direction. On the other hand, conventional DRAM (dynamic random access memory), SRAM (static random access memory) and MRAM (magnetic random access memory) show the writing time of .about.50 ns, .about.8 ns and .about.10 ns, respectively. Therefore, efforts should be made if PCRAM is to be used for high speed applications. [0005] In addition, there is a stability problem associated with thermal interference between adjacent memory cells. [0006] To store information in a binary form, memory cell exploits the difference in electrical resistance between crystalline and amorphous states. Specifically, in order to write `1` state (reset state) in a single cell, an electric voltage or current pulse is applied between the top and bottom electrodes contacting a phase change material, which induces direct or indirect heating on the phase change material for melting thereof. Upon termination of the electric pulse, the molten phase change material is quenched to an amorphous state, thereby writing the state `1` in a single cell. [0007] With density of PCRAM growing higher, binary data stored in amorphous memory cells may be corrupted with ease by unintended crystallization as a result of the heat generated in an adjoining memory cell which undergoes melting during a reset process thereof. [0008] Nitrogen or silicon may be added to a Ge--Sb--Te based alloy for raising the crystallization temperature thereof. However, the addition of impurities may slow the crystallization process (B. J. Kuh et al, EPCOS 2005). [0009] Further, integrating the memory device by sizing down the cell area is inherently bound by the limits of photolithographic techniques. In U.S. Pat. No. 5,414,271, it is disclosed that data can be stored in multi-bit forms by controlling the ratio between the amorphous and crystalline states in a single cell unit. However, it is extremely hard to control the dispersion between these two states. [0010] Accordingly, it is imperative to find a way for storing multi-bit information in a single cell unit. SUMMARY OF THE INVENTION [0011] It is, therefore, an object of the present invention to provide a non-volatile phase change memory cell devoid of at least one of the aforementioned problems, and a memory device using the same. [0012] In accordance with the present invention, there is provided a non-volatile phase change memory cell comprising a compound having the formula (Ge.sub.ASb.sub.BTe.sub.C).sub.1-X(R.sub.aS.sub.bTe.sub.C).sub.X, wherein Ge is germanium; Sb is antimony; Te is tellurium; R is an element selected from the elements belonging to the IVB group in the periodic table; S is an element selected from the elements belonging to the VB group in the periodic table; A, B, C, a, b and c are atomic mole ratios; x is a mole fraction in the range of 0 to 1; R.sub.aS.sub.bTe.sub.C has same crystal structure as Ge.sub.ASb.sub.BTe.sub.C; and at least one element of R and S has a higher atomic number and thus a smaller diatomic bond strength than that of the corresponding element in the GeSb portion of Ge--Sb--Te. BRIEF DESCRIPTION OF THE DRAWINGS [0013] The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which: [0014] FIG. 1 describes a schematic diagram of a phase change memory cell including a material in accordance with the present invention; [0015] FIG. 2 shows a planar view of 70 nm contact pore by SEM; [0016] FIG. 3 illustrates sectional SEM picture of a phase change memory cell including a material in accordance with the present invention; [0017] FIGS. 4a, 4b and 4c offer DC I-V characteristics of (Ge.sub.1Sb.sub.2Te.sub.4).sub.0.8(R.sub.1S.sub.2Te.sub.4).sub.0.2, (Ge.sub.1Sb.sub.2Te.sub.4).sub.0.9(R.sub.1S.sub.2Te.sub.4).sub.0.1 and Ge.sub.1Sb.sub.2Te.sub.4, respectively; [0018] FIGS. 5a, 5b and 5c delineate resistances of memory cells having (Ge.sub.1Sb.sub.2Te.sub.4).sub.0.8(R.sub.1S.sub.2Te.sub.4).sub.0.2, (Ge.sub.1Sb.sub.2Te.sub.4).sub.0.9(R.sub.1S.sub.2Te.sub.4).sub.0.1 and Ge.sub.1Sb.sub.2Te.sub.4, respectively; [0019] FIG. 6 demonstrates relationship between SET pulse voltage characteristics and SET pulse width; and [0020] FIG. 7 outlines change in sheet resistance with respect to the temperature of heat treatment. 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