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Perumal R. Subramoniam patents

Recent patents with Perumal R. Subramoniam listed as an inventor - additional entries may be under other spellings.

Perumal R. Subramoniam - Related organizations: Apple Inc. patents

Delaying cache data array updates

05/28/15 - 20150149722 - Systems, methods, and apparatuses for reducing writes to the data array of a cache. A cache hierarchy includes one or more L1 caches and a L2 cache inclusive of the L2 cache(s). When a request from the L1 cache misses in the L2 cache, the L2 cache sends a fill
Inventors: Hari S. Kannan, Brian P. Lilly, Perumal R. Subramoniam, Pradeep Kanapathipillai

Selective victimization in a multi-level cache hierarchy

05/28/15 - 20150149721 - Systems, methods, and apparatuses for implementing selective victimization to reduce power and utilized bandwidth in a multi-level cache hierarchy. Each set of an upper-level cache includes a counter that keeps track of the number of times the set was accessed. These counters are periodically decremented by another counter that tracks
Inventors: Hari S. Kannan, Brian P. Lilly, Perumal R. Subramoniam

Cache pre-fetch merge in pending request buffer

01/15/15 - 20150019824 - An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a pending request buffer and a control circuit. The pending request buffer may include a plurality of buffer entries. The control circuit may be coupled to the pending request buffer and may be configured
Inventors: Brian P. Lilly, Perumal R. Subramoniam, Prashant Jain

Cache policies for uncacheable memory requests

06/26/14 - 20140181403 - Multiple contiguous store misses are merged into larger blocks of data in the core interface unit before being sent to the L2 cache.
Inventors: Brian P. Lilly, Gerard R. Williams, Iii, Perumal R. Subramoniam, Pradeep Kanapathipillai

Prefetching across page boundaries in hierarchically cached processors

05/29/14 - 20140149632 - Processors and methods for preventing lower level prefetch units from stalling at page boundaries. An upper level prefetch unit closest to the processor core issues a preemptive request for a translation of the next page in a given prefetch stream. The upper level prefetch unit sends the translation to the
Inventors: Hari S. Kannan, Pradeep Kanapathipillai, Brian P. Lilly, Perumal R. Subramoniam, Mahnaz Sadoughi-yarandi

Coordinated prefetching in hierarchically cached processors

09/26/13 - 20130254485 - Processors and methods for coordinating prefetch units at multiple cache levels. A single, unified training mechanism is utilized for training on streams generated by a processor core. Prefetch requests are sent from the core to lower level caches, and a packet is sent with each prefetch request. The packet identifies
Inventors: Hari S. Kannan, Brian P. Lilly, Gerard R. Williams, Iii, Mahnaz Sadoughi-yarandi, Perumal R. Subramoniam, Pradeep Kanapathipillai

### Perumal R. Subramoniam patent invention listings

The bibliographic references displayed about Perumal R. Subramoniam's patents are for a recent sample of Perumal R. Subramoniam's publicly published patent applications. The inventor/author may have additional bibliographic citations listed at the is not associated or affiliated in any way with the author/inventor or the United States Patent/Trademark Office but is providing this non-comprehensive sample listing for educational and research purposes using public bibliographic data published and disseminated from the United States Patent/Trademark Office public datafeed. This information is also available for free on the website. If Perumal R. Subramoniam filed recent patent applications under another name, spelling or location then those applications could be listed on an alternate page. If no bibliographic references are listed here, it is possible there are no recent filings or there is a technical issue with the listing--in that case, we recommend doing a search on the website.


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