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Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patentsThe following is a sampling of recent Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patent applications (USPTO Patent Application #, Patent Title) sorted by month.
January 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20070008863 - Memory comprising a memory device and a write unit configured as a probe
20070011363 - Dual frequency first-in-first-out structure
20070002606 - Multi-context memory cell
20070002618 - Memory element, memory read-out element and memory cell
20070002619 - Bistable multivibrator with non-volatile state storage
December 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060290005 - Multi-chip device and method for producing a multi-chip device
20060294443 - On-chip address generation
20060286822 - Multi-chip device and method for producing a multi-chip device
20060278871 - Detecting and improving bond pad connectivity with pad check
20060282714 - Controllable delay device
20060282720 - Method for the automatic provision of repair position data of fuse elements in integrated memory circuit
20060274594 - Implementation of a fusing scheme to allow internal voltage trimming
November 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060268616 - Fuse memory cell with improved protection against unauthorized access
20060262613 - Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted
20060262614 - Integrated circuit, test system and method for reading out an error datum from the integrated circuit
20060265548 - Method for operating a pmc memory cell and cbram memory circuit
20060259711 - Technique to read special mode register
20060250868 - Electronic component with improved precharging
20060250881 - Memory arrangement having a plurality of ram chips
20060246726 - Making contact with the emitter contact of a semiconductor
October 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060242492 - Method and apparatus for masking known fails during memory tests readouts
20060233005 - Device in a memory circuit for definition of waiting times
20060233031 - Synchronous ram memory circuit
20060233037 - Method and apparatus for operating electronic semiconductor chips via signal lines
20060227627 - Buffer component for a memory module, and a memory module and a memory system having such buffer component
20060221555 - Solid electrolyte memory element and method for fabricating such a memory element
20060221663 - Electronic device with a memory cell
20060221690 - Test mode for detecting a floating word line
September 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060208357 - Integrated device and electronic system
20060202317 - Method for mcp packaging for balanced performance
20060203559 - Memory device with customizable configuration
20060203567 - Integrated memory circuit and method for repairing a single bit error
20060205111 - Method for producing chip stacks and chip stacks formed by integrated devices
20060197566 - Dll circuit for providing an output signal with a desired phase shift
20060197567 - Dll circuit for providing an adjustable phase relationship with respect to a periodic input signal
20060198211 - Test system for testing integrated circuits and a method for configuring a test system
20060198231 - Pulse controlled word line driver
August 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060193184 - Hub module for connecting one or more memory chips
20060193194 - Data strobe synchronization for dram devices
20060190674 - Hub chip for connecting one or more memory chips
20060181916 - Non-volatile memory cell for storage of a data item in an integrated circuit
20060181956 - Memory device having components for transmitting and receiving signals synchronously
20060176725 - Pmc memory circuit and method for storing a datum in a pmc memory circuit
20060170456 - Driver circuit for binary signals
20060170485 - Integrated charge pump
20060171220 - Test data topology write to memory using latched sense amplifier data and row address scrambling
20060171233 - Near pad ordering logic
20060171234 - Ddr ii dram data path
July 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060162957 - Printed circuit board, printed circuit module and method for producing a printed circuit board
20060164116 - Internal reference voltage generation for integrated circuit testing
20060157866 - Signal redistribution using bridge layer for multichip module
20060161743 - Intelligent memory array switching logic
20060152957 - Circuit arrangement and method for setting operating parameters in a ram module
20060152984 - Memory component and addressing of memory cells
20060152988 - Memory component having a novel arrangement of the bit lines
20060146593 - Method and circuit for reading a dynamic memory circuit
20060150039 - Input circuit for an integrated circuit
June 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060140025 - Method for operating a semiconductor memory apparatus, and semiconductor memory system
20060140039 - Voltage supply circuit, in particular for a dram memory circuit, as well as a method for controlling a supply source
20060133159 - Method for transmission and reception of a data signal on a line pair, as well as a transmission and reception circuit for this purpose
20060133172 - Apparatus and method for writing to and/or reading from a memory cell in a semiconductor memory
20060133186 - Memory access using multiple activated memory cell rows
20060125520 - Method to improve current and slew rate ratio of off-chip drivers
20060126407 - Methods for repairing and for operating a memory component
20060126413 - Memory circuit and method for reading out a memory datum from such a memory circuit
20060129740 - Memory device, memory controller and method for operating the same
20060118851 - Memory cell and integrated memory circuit
20060119406 - Flip-flop with additional state storage in the event of turn-off
20060120200 - Integrated dram memory device
20060121257 - Method for producing a rewiring printed circuit board
May 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060109731 - Twin-cell bit line sensing configuration
20060109869 - Method and circuit arrangements for adjusting signal propagation times in a memory system
20060112230 - Integrated memory device and memory module
20060112239 - Memory device for use in a memory module
20060107026 - Memory access using multiple sets of address/data lines
20060095652 - Memory device and method for receiving instruction data
April 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060087895 - Memory circuit with flexible bitline-related and/or wordline-related defect memory cell substitution
20060085705 - Memory circuit comprising an initialization unit, and method for optimizing data reception parameters in a memory controller
20060076996 - Delay circuit with accurate time to frequency conversion
20060077730 - Memory control module and method for operating a memory control module
20060071257 - Gate layer diode method and apparatus
20060071689 - Circuit and method for generating an output signal
March 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060067156 - Memory device, memory controller and memory system having bidirectional clock lines
20060067157 - Memory system with two clock lines and a memory device
20060069880 - Apparatus for controlling access, by processing devices, to memories in an embedded system
20060064620 - Self test for the phase angle of the data read clock signal dqs
20060054812 - Method and apparatus for characterizing a recess located on a surface of a substrate
20060056255 - Semiconductor memory apparatus and method for operating a semiconductor memory apparatus
20060059394 - Loop-back method for measuring the interface timing of semiconductor memory devices using the normal mode memory
20060059397 - Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods
20060049511 - Integrated semiconductor circuit and method for producing an integrated semiconductor circuit
20060049515 - Memory module having memory chips protected from excessive heat
20060049967 - Code driver for a memory controller
20060050546 - Memory circuit having memory cells which have a resistance memory element
20060050572 - Memory circuit with supply voltage flexibility and supply voltage adapted performance
20060050577 - Memory module with programmable fuse element
February 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060031620 - Memory controller with a plurality of parallel transfer blocks
20060026475 - Semiconductor circuit device and a system for testing a semiconductor apparatus
January 2006 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies patents
20060018165 - Digital ram memory circuit with an expanded command structure
20060006411 - Method for producing a package for an electronic circuit and a substrate for a package
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This listing is an abstract for educational and research purposes is only meant as a recent sample of applications filed, not a comprehensive history. Freshpatents.com is not affiliated or associated with Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies in any way and there may be associated servicemarks. This data is also published to the public by the USPTO and available for free on their website. Note that there may be alternative spellings for Patterson & Sheridan, LLP Gero Mcclellan / Infineon Technologies with additional patents listed. Browse our Agent directory for other possible listings.
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