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Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

The following is a sampling of recent Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patent applications (USPTO Patent Application #, Patent Title) sorted by month.

January 2008 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20080025120 - Temperature update masking to ensure correct measurement of temperature when references become unstable
20080019163 - Method and memory circuit for operating a resistive memory cell
20080012598 - Apparatus and method for controlling a driver strength
20080007569 - Control protocol and signaling in a new memory architecture
20080008012 - Implementation of a fusing scheme to allow internal voltage trimming
20080010418 - Method for accessing a non-volatile memory via a volatile memory interface
20080010419 - System and method for issuing commands
20080010420 - Method for accessing control registers via a memory device
20080010438 - Memory with an output register for test data and process for testing a memory and memory module
20080002323 - Method and protective circuit against overvoltage
20080002486 - Method for accessing a memory
20080002515 - Memory with alterable column selection time

December 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070288716 - Memory system with a retiming circuit and a method of exchanging data and timing signals between a memory controller and a memory device
20070280007 - Memory device, memory system and method of operating such
20070280011 - Integrated electrical module with regular and redundant elements

November 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070269598 - Method, apparatus and starting material for providing a gaseous precursor
20070258307 - Memory circuit and method for refreshing dynamic memory cells
20070258552 - Data receiver with clock recovery circuit
20070260955 - Test auxiliary device in a memory module

October 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070247929 - Memory device and method of operating such
20070245036 - Illegal commands handling at the command decoder stage
20070230082 - Integrated circuit having a plurality of externally fed power supply systems
20070230266 - Methods of ddr receiver read re-synchronization

September 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070223293 - Parallel read for front end compression mode
20070223299 - Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a temperature of a memory
20070226553 - Multiple banks read and data compression for back end test
20070226591 - Integrated device for simplified parallel testing, test board for testing a plurality of integrated devices, and test system and tester unit
20070210297 - Electrical structure with a solid state electrolyte layer, memory with a memory cell and method for fabricating the electrical structure
20070210433 - Integrated device having a plurality of chip arrangements and method for producing the same
20070211514 - Memory circuit, method for operating a memory circuit, memory device and method for producing a memory device

August 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070195580 - Memory circuit having a resistive memory cell and method for operating such a memory circuit
20070195611 - Programmable structure, a memory, a display and a method for reading data from a memory cell
20070189059 - Memory device and method for reading data
20070192754 - Method for treating design errors of a layout of an integrated circuit
20070186061 - Shared interface for components in an embedded system
20070186124 - Data handover unit for transferring data between different clock domains

July 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070171697 - Cbram memory device and method for writing to a resistive memory cell in a cbram memory device
20070171698 - Memory circuit including a resistive memory element and method for operating such a memory circuit
20070174602 - Method of system booting with a direct memory access in a new memory architecture
20070165466 - Memory device comprising fuse memory elements
20070165469 - Test parallelism increase by tester controllable switching of chip select groups
20070165479 - Local wordline driver scheme to avoid fails due to floating wordline in a segmented wordline driver scheme
20070153601 - Integrated circuit and method of operating such a circuit

June 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070147102 - Memory with resistance memory cell and evaluation circuit
20070150792 - Memory module comprising a plurality of memory devices
20070140023 - Integrated dynamic random access memory chip
20070132616 - Correction of static mismatch errors in a d/a converter
20070133730 - Apparatus and method for avoiding steady-state oscillations in the generation of clock signals

May 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070109878 - Memory device with improved writing capabilities
20070104292 - Timing recovery phase locked loop

April 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070090527 - Integrated chip device in a package
20070091711 - Method of transferring signals between a memory device and a memory controller
20070084944 - Methods for aligning a device and for stacking two devices in an aligned manner and device for improved stacking
20070085561 - Output circuit for a hub chip for outputting a high-frequency signal, a hub chip, a memory module and a method for operating an output circuit
20070075122 - Method for fabricating a chip module and a device module fabricated therefrom
20070076504 - Memory device having low vpp current consumption

March 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070046329 - Differential duty cycle restoration
20070046344 - Delay locked loop using a fifo circuit to synchronize between blender and coarse delay control signals
20070047291 - Integrated memory circuit comprising a resistive memory element and a method for manufacturing such a memory circuit

February 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070041251 - Electrical circuit and a method for operating a programmable metallization cell
20070035007 - Differential chip performance within a multi-chip package
20070035326 - Memory chip and method for operating a memory chip
20070038804 - Testmode and test method for increased stress duty cycles during burn in
20070030722 - Memory cell
20070030738 - Technique to suppress leakage current
20070030751 - Semiconductor memory having a short effective word line cycle time and method for reading data from a semiconductor memory of this type
20070023886 - Method for producing a chip arrangement, a chip arrangement and a multichip device
20070023898 - Integrated circuit chip and integrated device
20070025163 - Maintaining internal voltages of an integrated circuit in response to a clocked standby mode
20070028030 - Device for transmitting data between memories

January 2007 - Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda patents

20070018715 - Clocked standby mode with maximum clock frequency
20070019488 - Temperature update masking to ensure correct measurement of temperature when references become unstable
20070019489 - Disabling clocked standby mode based on device temperature



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