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Pattern verification method, program thereof, and manufacturing method of semiconductor deviceRelated Patent Categories: Data Processing: Design And Analysis Of Circuit Or Semiconductor Mask, Circuit Design, Testing Or Evaluating, Design Verification (e.g., Wiring Line Capacitance, Fan-out Checking, Minimum Path Width)Pattern verification method, program thereof, and manufacturing method of semiconductor device description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070050741, Pattern verification method, program thereof, and manufacturing method of semiconductor device. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2005-244448, filed Aug. 25, 2005, the entire contents of which are incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to an optical and X-ray lithography technology in manufacture of a semiconductor integrated circuit, a liquid crystal panel or the like, and more particularly to a verification method (lithography simulation) of a semiconductor integrated circuit, a verification program thereof, and a manufacturing method of a semiconductor device. [0004] 2. Description of the Related Art [0005] In recent years, as a semiconductor integrated circuit manufacturing technology has been sophisticated and a difficulty level has been increased, it is becoming very hard to increase a process yield (a ratio of non-defective chips per wafer), and a critical pattern exists even if design rules are kept, resulting in a decrease in a process yield. Therefore, in order to increase a process yield, it has begun to attach importance to performing lithography simulation with respect to a design layout pattern before making a mask to reduce hot spots (critical patterns). [0006] For example, Jpn. Pat. Appln. KOKAI Publication No. 2003-92237 provides means for setting semiconductor process conditions and mask pattern shapes avoiding occurrence of crystal defects based on simulation and setting robust semiconductor process conditions with respect to unevenness or fluctuations in semiconductor manufacturing process conditions or unevenness in mask pattern shapes. [0007] However, a recent lithography verification tool takes the same amount of time as an optical proximity correction (OPC) processing time even under one set of conditions, and cannot feed back an error result to a design layout in a realistic turnaround time (TAT). [0008] Therefore, there has been demanded realization of a semiconductor integrated circuit pattern verification method which can shorten a turnaround time, a program which allows a computer to execute this method, and a manufacturing method of a semiconductor device which realizes a pattern verified by this method and program on a semiconductor substrate. BRIEF SUMMARY OF THE INVENTION [0009] According to a first aspect of the invention, there is provided an integrated circuit pattern verification method which includes: [0010] extracting a pattern which is not greater than a preset pattern size; [0011] extracting a pattern edge as a target of lithography simulation from the extracted pattern; and [0012] performing the lithography simulation on the extracted pattern edge to verify the pattern. [0013] According to a second aspect of the invention, there is provided an integrated circuit pattern verification method which includes: [0014] sorting integrated circuit patterns into a plurality of pattern groups based on pattern sizes or pattern types; and [0015] performing lithography simulation on the plurality of sorted pattern groups while changing respective conditions to verify the patterns. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING [0016] FIG. 1 is a view showing a flowchart of a pattern verification method according to a first embodiment; [0017] FIG. 2 is a view showing an example of wiring lines according to the first embodiment; [0018] FIG. 3 is a view illustrating extraction of wiring lines having widths which are not greater than a preset size; [0019] FIG. 4 is a view illustrating extraction of wiring lines having spaces which are not greater than a preset size; [0020] FIG. 5 is a view illustrating target edges in lithography simulation; Continue reading about Pattern verification method, program thereof, and manufacturing method of semiconductor device... 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