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Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structureRelated Patent Categories: Semiconductor Device Manufacturing: Process, Coating With Electrically Or Thermally Conductive Material, To Form Ohmic Contact To Semiconductive Material, Contacting Multiple Semiconductive Regions (i.e., Interconnects), Multiple Metal Levels, Separated By Insulating Layer (i.e., Multiple Level Metallization), With Formation Of Opening (i.e., Viahole) In Insulative LayerPattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060141774, Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of application Ser. No. 10/442,960, filed May 22, 2003, and claims priority to the Japanese Application No. 2002-309416, filed on Oct. 24, 2002, The entire content of the parent application is incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a pattern transfer mask for use in manufacture of a semiconductor device including dual damascene structures, and further relates to a method of manufacturing a semiconductor device using the pattern transfer mask. [0004] 2. Description of the Background Art [0005] Copper (Cu) dual damascene structures have conventionally been employed for multilevel interconnection for semiconductor devices. Such structures are formed as described below. First, via holes are formed in an oxide film of a substrate. Thereafter, resist is coated entirely over the oxide film, and is patterned into a pattern that corresponds to trenches by exposure to light and development. An anti-reflection film may be deposited by coating or the like before coating resist for via holes or trenches. Next, the oxide film is etched using the patterned resist as a mask, thereby forming trenches. The trenches are formed over the via holes. Then, a Cu film is plated in the via holes and trenches, thereby completing a dual damascene structure. [0006] Such dual damascene structure is introduced by Japanese Patent Application Laid-Open No. 2000-58647 (FIG. 4), for example. [0007] With the above-described conventional method, resist is coated entirely over the oxide film in which the via holes are formed or over the anti-reflection film, and thus collects in the via holes. At this time, the thickness of resist (i.e., the thickness based on the surface of part of the oxide film where no via hole is formed) tends to be small over the via holes. Besides, the resist collects in the via holes in different manners depending on the layout of the via holes. Thus, the resist varies in thickness in an area where no via hole is formed, an area where many via holes are opened and an area where less via holes are opened. [0008] Likewise, in the case where the anti-reflection film is deposited by coating on the oxide film in which via holes are formed, the anti-reflection film varies in thickness depending on the layout of the via holes. [0009] If resist varies in thickness in light transfer, a finished dimension of a resist pattern after development varies due to standing wave effect (interference effect) and bulk effect (absorbing effect) even with the same amount of exposure. That is, a problem arises in that a trench pattern of a desired dimension cannot be obtained resulting from the presence and layout of via holes. [0010] Likewise, when the anti-reflection film varies in thickness, a trench pattern of a desired dimension cannot be obtained resulting from variations in reflectance. [0011] Further, exposure light generally varies in reflectance in an area where via holes are present and an area where via holes are absent, which causes effective exposure to vary even with the same amount of exposure. In this case, a trench pattern of a desired dimension cannot be obtained, similarly to the above-described cases. [0012] As a result of the above-described drawback, if finished trenches are narrower than desired, increase in wiring resistance and breaks easily occur. Conversely, if finished trenches are wider than desired, wiring resistance becomes lower than a design value and adjacent interconnect lines are short-circuited. That is, designed operations cannot be obtained in semiconductor devices. SUMMARY OF THE INVENTION [0013] An object of the present invention is to provide a pattern transfer mask capable of reducing the above-described pattern abnormalities in the vicinity of holes in a resist pattern after development and further, a method of manufacturing a semiconductor device using the pattern transfer mask and a computer program for making a mask pattern for the pattern transfer mask. [0014] According to the present invention, the pattern transfer mask is for transferring a pattern to resist when manufacturing a semiconductor device. The semiconductor device includes, in one layer, a plurality of dual damascene structures each including at least one hole, a trench extending over the at least one hole and a conductive material buried in the at least one hole and the trench. The pattern transfer mask is used when patterning the resist for forming the trenches. The pattern transfer mask includes a light shielding pattern subjected to one of undersizing and oversizing in the vicinity of a portion that corresponds to each of the holes and a light transmitting pattern having higher light transmittance than the light shielding pattern. [0015] Pattern abnormalities (shape abnormalities) can be reduced in the vicinity of the holes in the developed resist pattern, which thus can reduce shape abnormalities of the trenches and the conductive material buried in the trenches. [0016] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0017] FIG. 1 is a layout design view of a semiconductor device including dual damascene structures, illustrating a pattern transfer mask according to a first preferred embodiment of the present invention; [0018] FIG. 2 is a sectional view illustrating the dual damascene structure; [0019] FIG. 3 is a plan view illustrating a substrate after forming via holes therein; [0020] FIG. 4 is a sectional view illustrating a method of forming trenches; Continue reading about Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure... Full patent description for Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure or other areas of interest. ### Previous Patent Application: Methods of forming interconnection lines in semiconductor devices Next Patent Application: Manufacturing method of semiconductor device Industry Class: Semiconductor device manufacturing: process ### FreshPatents.com Support Thank you for viewing the Pattern transfer mask related to formation of dual damascene structure and method of forming dual damascene structure patent info. IP-related news and info Results in 0.10354 seconds Other interesting Feshpatents.com categories: Canon USA , Celera Genomics , Cephalon, Inc. , Cingular Wireless , Clorox , Colgate-Palmolive , Corning , Cymer , 174 |
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